Datasheet

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 71 of 108
TIMER2 OR WATCHDOG TIMER
Timer2 has two modes of operation, normal mode and
watchdog mode. The watchdog timer is used to recover
from an illegal software state. When enabled, it requires
periodic servicing to prevent it from forcing a reset of the
processor.
Timer2 reloads the value from T2LD either when Timer2
overflows or immediately when T2CLRI is written.
Normal Mode
Timer2 in normal mode is identical to Timer0 in the 16-bit
mode of operation, except for the clock source. The clock
source is the low power, 32.768 kHz oscillator scalable by a
factor of 1, 16, or 256.
Watchdog Mode
Watchdog mode is entered by setting T2CON[Bit 5]. Timer2
decrements from the timeout value present in the T2LD register
until zero. The maximum timeout is 512 seconds, using a
maximum prescaler/256 and full scale in T2LD.
User software should not configure a timeout period of less
than 30 ms. This is to avoid any conflict with Flash/EE memory
page erase cycles that require 20 ms to complete a single page
erase cycle and kernel execution.
If T2VAL reaches 0, a reset or an interrupt occurs, depending
on T2CON[1]. To avoid a reset or an interrupt event, any value
must be written to T2CLRI before T2VAL reaches zero. This
reloads the counter with T2LD and begins a new timeout period.
When watchdog mode is entered, T2LD and T2CON are
write protected. These two registers cannot be modified until
a power-on reset event resets the watchdog timer. After any
other reset event, the watchdog timer continues to count. To
avoid an infinite loop of watchdog resets, configure the
watchdog timer in the initial lines of user code. User software
should configure a minimum timeout period of 30 ms only.
Timer2 halts automatically during JTAG debug access and only
recommences counting after JTAG relinquishes control of the
ARM7 core. By default, Timer2 continues to count during
power-down. To disable this, set Bit 0 in T2CON. It is
recommended that the default value be used, that is, that the
watchdog timer continues to count during power-down.
Timer2 Interface
The Timer2 interface consists of four MMRs.
• T2CON is the configuration MMR, described in (Table 82).
• T2LD and T2VAL are 16-bit registers (Bit 0 to Bit 15) and
hold 16-bit, unsigned integers. T2VAL is read only.
• T2CLRI is an 8-bit register. Writing any value to this
register clears the Timer2 interrupt in normal mode or
resets a new timeout period in watchdog mode.
Timer2 Load Register
Name: T2LD
Address: 0xFFFF0360
Default value: 0x3BF8
Access: Read and write
Function: This 16-bit MMR holds the Timer2
reload value.
Timer2 Clear Register
Name: T2CLRI
Address: 0xFFFF036C
Access: Write only
Function: This 8-bit, write-only MMR is written (with
any value) by user code to refresh (reload)
Timer2 in watchdog mode to prevent a
watchdog timer reset event.
Timer2 Value Register
Name: T2VA L
Address: 0xFFFF0364
Default value: 0x3BF8
Access: Read only
Function: This 16-bit, read-only MMR holds the
current Timer2 count value.
PRESCALER
1, 16, 256
TIMER2 IRQ
WATCHDOG RESET
16-BIT
UP/DOWN COUNTER
32.768kHz
16-BIT LOAD
TIMER2
VALUE
07079-019
Figure 25. Timer2 Block Diagram