Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 7 of 108
Parameter Test Conditions/Comments Min Typ Max Unit
External Reference Input
Range
12
0.1 AVDD V
V
REF
Divide-by-2 Initial Error
1
0.1 %
DAC CHANNEL SPECIFICATIONS R
L
= 5 kΩ, C
L
= 100 pF
Voltage Range 0 V
REF
V
0 AVDD − 0.2 V
DAC 12-BIT MODE
DC Specifications
13
Resolution 12 Bits
Relative Accuracy ±2 LSB
Differential Nonlinearity Guaranteed monotonic ±0.2 ±1 LSB
Offset Error 1.2 V internal reference ±2 ±15 mV
Gain Error V
REF
range (reference = 1.2 V) ±1 %
AVDD range ±1 %
Gain Error Mismatch 0.1 % of full
scale on
DAC
DAC 16-BIT MODE
1
Only monotonic to 14 bits
DC Specifications
14
Resolution 14 Bits
Relative Accuracy For 14-bit resolution ±3 LSB
Differential Nonlinearity Guaranteed monotonic (14 bits) ±0.5 ±1 LSB
Offset Error 1.2 V internal reference ±2 ±15 mV
Gain Error V
REF
range (reference = 1.2 V) ±1 %
AVDD range
±1
%
Gain Error Mismatch 0.1 % of full
scale on
DAC
DAC AC CHARACTERISTICS
Voltage Output Settling Time 10 µs
Digital-to-Analog Glitch Energy 1 LSB change at major carry
(where maximum number of
bits simultaneously change in
the DAC0DAT register)
±20 nV-sec
TEMPERATURE SENSOR
1, 15
After user calibration
Accuracy MCU in power-down or standby
mode
±4 °C
Voltage Output at 0°C Typical value 96 mV
Voltage Tempco Typical value 0.28 mV/°C
Thermal Impedance 48-lead LFCSP 27 °C/W
48-lead LQFP 55 °C/W
32-lead LFCSP 30 °C/W
POWER-ON RESET (POR)
POR Trip Level
1
Refers to voltage at DVDD pin
Power-on level 2.0 V
Power-down level 2.25 V
RESET
Timeout from POR Maximum supply ramp between
1.8 V and 2.25 V; after POR trip,
DVDD must reach 2.25 V within
this time limit
128 ms