Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 66 of 108
TIMERS
The ADuC706x features four general-purpose timer/counters.
• Timer0
• Timer1 or wake-up timer
• Timer2 or watchdog timer
• Timer3
The four timers in their normal mode of operation can be either
free running or periodic.
In free running mode, the counter decrements/increments from
the maximum or minimum value until zero/full scale and starts
again at the maximum or minimum value.
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR) until zero/full scale and
starts again at the value stored in the load register. Note that the
TxLD MMR should be configured before the TxCON MMR.
The timer interval is calculated as follows:
If the timer is set to count down then
Interval = (TxLD x Prescaler) / Source Clock
If the timer is set to count up then
Interval = ((Full Scale - TxLD) x Prescaler) / Source Clock.
The value of a counter can be read at any time by accessing its
value register (TxVAL). Timers are started by writing in the
control register of the corresponding timer (TxCON).
In normal mode, an IRQ is generated each time that the value
of the counter reaches zero (if counting down) or full scale (if
counting up). An IRQ can be cleared by writing any value to the
clear register of the particular timer (TxCLRI).
Table 78. Timer Event Capture
Bit Description
0 Reserved
1 Timer0
2 Timer1 or wake-up timer
3 Timer2 or watchdog timer
4 Timer3
5 Reserved
6 Reserved
7 Reserved
8 ADC
9 UART
10 SPI
11 XIRQ0
12 XIRQ1
13 I
2
C master
14
I
2
C slave
15 PWM
16 XIRQ2 (GPIO IRQ2)
17 XIRQ3 (GPIO IRQ3)
HR:MIN:SEC: 1/128 FORMAT
To use the timer in Hr : Min : Sec : hundreds format the 32768
kHz clock and prescaler of 256 should be selected. The
hundreds field does not represent milliseconds but 1/128 of a
second (256/32768).The bits representing the Hour, minute and
second are not consecutive in the register. This arrangement
applies to TxLd and TxVAL when using the Hr : Min : Sec :
hundreds format as set in TxCON[5:4]. See Table 79 for more
details.
Table 79. Hr:Min:Sec: hundreds format
Bit Value Description
31:24 0 to 23 or 0 to 255 Hours
23:22 0 Reserved
21:16 0 to 59 Minutes
15:14 0 Reserved
13:8 0 to 59 Seconds
7 0 Reserved
6:0 0 to 127 1/128 of second