Datasheet

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 59 of 108
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 15 interrupt sources on the ADuC706x that are con-
trolled by the interrupt controller. All interrupts are generated
from the on-chip peripherals, except for the software interrupt
(SWI), which is programmable by the user. The ARM7TDMI
CPU core recognizes interrupts as one of two types only: a
normal interrupt request (IRQ) or a fast interrupt request
(FIQ). All the interrupts can be masked separately.
The control and configuration of the interrupt system are
managed through a number of interrupt related registers. The
bits in each IRQ and FIQ register represent the same interrupt
source, as described in Table 65.
Each ADuC706x contains a vectored interrupt controller (VIC)
that supports nested interrupts up to eight levels. The VIC also
allows the programmer to assign priority levels to all interrupt
sources. Interrupt nesting needs to be enabled by setting the
ENIRQN bit in the IRQCONN register. A number of extra
MMRs are used when the full vectored interrupt controller is
enabled.
Immediately save IRQSTA/FIQSTA upon entering the interrupt
service routine (ISR) to ensure that all valid interrupt sources
are serviced.
Table 65. IRQ/FIQ MMR Bit Designations
Bit Description Comments
0 All interrupts OR’ed
(FIQ only)
This bit is set if any FIQ is active
1 Software interrupt User programmable interrupt
source
2 Undefined This bit is not used
3
Timer0
General-Purpose Timer0
4 Timer1 or wake-up
timer
General-Purpose Timer1 or
wake-up timer
5 Timer2 or watchdog
timer
General-Purpose Timer2 or
watchdog timer
6 Timer3 or STI timer General-Purpose Timer3
7 Undefined This bit is not used
8 Undefined This bit is not used
9 Undefined This bit is not used
10 ADC ADC interrupt source bit
11
UART
UART interrupt source bit
12
SPI
SPI interrupt source bit
13 XIRQ0 (GPIO IRQ0) External Interrupt 0
14 XIRQ1 (GPIO IRQ1) External Interrupt 1
15 I
2
C master IRQ I
2
C master interrupt source bit
16 I
2
C slave IRQ I
2
C slave interrupt source bit
17 PWM PWM trip interrupt source bit
18 XIRQ2 (GPIO IRQ2) External Interrupt 2
19 XIRQ3 (GPIO IRQ3) External Interrupt 3
IRQ
The IRQ is the exception signal to enter the IRQ mode of the
processor. It services general-purpose interrupt handling of
internal and external events.
All 32 bits are logically OR’ed to create a single IRQ signal to
the ARM7TDMI core. The four 32-bit registers dedicated to
IRQ are described in the following sections.
IRQSIG
IRQSIG reflects the status of the different IRQ sources. If a
peripheral generates an IRQ signal, the corresponding bit in
the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear
when the interrupt in the particular peripheral is cleared. All
IRQ sources can be masked in the IRQEN MMR. IRQSIG is
read only.
IRQSIG Register
Name: IRQSIG
Address: 0xFFFF0004
Default value: Undefined
Access: Read only
IRQEN
IRQEN provides the value of the current enable mask. When a
bit is set to 1, the corresponding source request is enabled
to create an IRQ exception. The IRQEN register cannot be used
to disable an interrupt. Clear to 0 has no effect.
IRQEN Register
Name: IRQEN
Address: 0xFFFF0008
Default value: 0x00000000
Access: Read and write
IRQCLR
IRQCLR is a write-only register that allows the IRQEN register
to clear to mask an interrupt source. Each bit that is set to 1
clears the corresponding bit in the IRQEN register without
affecting the remaining bits. The pair of registers, IRQEN and
IRQCLR, allows independent manipulation of the enable mask
without requiring an atomic read-modify-write. Clear to 0 has
no effect.