Datasheet

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 58 of 108
NONVOLATILE FLASH/EE MEMORY
The ADuC706x incorporates Flash/EE memory technology
on chip to provide the user with nonvolatile, in-circuit reprogram-
mable memory space.
Like EEPROM, flash memory can be programmed in-system
at a byte level, although it must first be erased. The erase is
performed in page blocks. As a result, flash memory is often
and, more correctly, referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the
ideal memory device that includes nonvolatility, in-circuit
programmability, high density, and low cost. Incorporated in
the ADuC706x, Flash/EE memory technology allows the user
to update program code space in-circuit, without the need to
replace one time programmable (OTP) devices at remote
operating nodes.
The ADuC706x contains a 32 kB array of Flash/EE memory.
The lower 30 kB are available to the user and the upper 2 kB
contain permanently embedded firmware, allowing in-circuit
serial download. These 2 kB of embedded firmware also contain
a power-on configuration routine that downloads factory-
calibrated coefficients to the various calibrated peripherals
(such as ADC, temperature sensor, and band gap references).
This 2 kB embedded firmware is hidden from user code.
FLASH/EE MEMORY RELIABILITY
The Flash/EE memory arrays on the parts are fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as
• Initial page erase sequence
• Read/verify sequence for a single Flash/EE
• Byte program sequence memory
• Second read/verify sequence endurance cycle
In reliability qualification, every half word (16-bit wide)
location of the three pages (top, middle, and bottom) in the
Flash/EE memory is cycled 10,000 times from 0x0000 to
0xFFFF. The Flash/EE memory endurance qualification is
carried out in accordance with JEDEC Retention Lifetime
Specification A117 over the industrial temperature range of
−40°C to +125°C. The results allow the specification of a
minimum endurance figure over a supply temperature of
10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the parts are
qualified in accordance with the formal JEDEC Retention
Lifetime Specification A117 at a specific junction temperature
(T
J
= 85°C). As part of this qualification procedure, the Flash/
EE memory is cycled to its specified endurance limit, described
previously, before data retention is characterized. This means
that the Flash/EE memory is guaranteed to retain its data for its
fully specified retention lifetime every time that the Flash/EE
memory is reprogrammed. Also note that retention lifetime,
based on activation energy of 0.6 eV, derates with T
J
, as shown
in Figure 22.
150
300
450
600
30 40 55 70 85 100 125 135 150
RETENTION (Years)
0
JUNCTION TEMPERATURE (°C)
07079-016
Figure 22. Flash/EE Memory Data Retention
PROGRAMMING
The 30 kB of Flash/EE memory can be programmed in-circuit,
using the serial download mode or the provided JTAG mode.
Serial Downloading (In-Circuit Programming)
The ADuC706x facilitates code download via the standard
UART serial port. The parts enter serial download mode after a
reset or power cycle if the NTRST/
BM
pin is pulled low
through an external 1 kΩ resistor. When in serial download
mode, the user can download code to the full 30 kB of Flash/EE
memory while the device is in-circuit in its target application
hardware. An executable PC serial download is provided as part
of the development system for serial downloading via the UART.
When the ADuC706x enters download mode, the user should
be aware that the internal watchdog is enabled with a time-out
period of 2 minutes. If the flash erase/write sequence is not
completed in this period, a reset occurs.
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate
code download and debug.