Datasheet

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Table Of Contents

Features
Applications
General Description
Revision History
Functional Block Diagram
Specifications
- Electrical Specifications
- Timing Specifications
  - I2C Timing
  - SPI Timing
Absolute Maximum Ratings
- ESD Caution
Pin Configurations and Function Descriptions
Terminology
Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
  - ARM7 Exceptions
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
  - RSTSTA Register
  - RSTCLR Register
Oscillator, PLL, and Power Control
- Clocking System
  - External Crystal Selection
  - External Clock Selection
- Power Control System
  - Power and Clock Control Registers
ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- Example Application Circuits
DAC Peripherals
- DAC
  - Op Amp Mode
- MMR Interface
  - DAC0CON Register
  - DAC0DAT Register
- Using the DAC
Nonvolatile Flash/EE Memory
- Flash/EE Memory Reliability
- Programming
  - Serial Downloading (In-Circuit Programming)
  - JTAG Access
Processor Reference Peripherals
- Interrupt System
- IRQ
- Fast Interrupt Request (FIQ)
- Programmed Interrupts
  - SWICFG
    - SWICFG Register
- Vectored Interrupt Controller (VIC)
- VIC MMRs
Timers
- HR:MIN:SEC: 1/128 Format
- Timer0
- Timer1 or Wake-Up Timer
- Timer2 or Watchdog Timer
- Timer3
Pulse-Width Modulator
- Pulse-Width Modulator General Overview
UART Serial Interface
- Baud Rate Generation
  - Normal 450 UART Baud Rate Generation
  - ADuC706x Fractional Divider
- UART Register Definitions
I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
  - Slave Mode
  - Master Mode
- I2C Registers
Serial Peripheral Interface
- MISO (Master In, Slave Out) Pin
- MOSI (Master Out, Slave In) Pin
- SCLK (Serial Clock I/O) Pin
- Slave Select (P0.0/) Input Pin
- Configuring External Pins for SPI Functionality
- SPI Registers
General-Purpose I/O
- GPxCON Registers
- GPxDAT Registers
- GPxSET Registers
- GPxCLR Registers
- GPxPAR Registers
  - GP0CON1 Control Registers
Hardware Design Considerations
- Power Supplies
Outline Dimensions
- Ordering Guide

Data Sheet ADuC7060/ADuC7061

Rev. D | Page 53 of 108

Primary Channel ADC Comparator Threshold Register

Name: ADC0ATH

Address: 0xFFFF054C

Default value: 0x00000000

Access: Read and write

Function:

This 32-bit MMR holds the threshold value for

the accumulator comparator of the primary

channel. When the accumulator value in

ADC0ACC exceeds the value in ADC0ATH,

the ADC0ATHEX bit in ADCSTA is set. This

causes an interrupt if the corresponding bit in

ADCMSKI is also enabled.

Table 61. ADC0ATH MMR Bit Designations

Bit Description

31:0 ADC0 32-bit comparator threshold register of the

accumulator.

INTERRUPT

(ADC0OVR)

|ABSVAL|

INTERRUPT

(ADC0RDY)

(READABLE)

CLEAR

(READABLE)

OPTION: UP/RESET

INTERRUPT

(ADC0ATHEX)

INTERRUPT

(ADC0THEX)

ADC0ATH

≥

ADC0ACC

ACCUMULATOR

ADC

ADC0THC

≥≥

ADC0TH

ADC0THV

UP/DOWN

ADC0RCV

COUNTER

ADC0RCR

(DEFAULT = 1)

ADC

PRIMARY

ADC

ADC0

ADC1

FAST

OVERRANGE

07079-011

Figure 17. Primary ADC Accumulator/Comparator/Counter Block Diagram