Datasheet

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 52 of 108
Primary Channel ADC Threshold Register
Name: ADC0TH
Address: 0xFFFF053C
Default value: 0x0000
Access: Read and write
Function:
This 16-bit MMR sets the threshold against
which the absolute value of the primary ADC
conversion result is compared. In unipolar
mode, ADC0TH[15:0] are compared, and in
twos complement mode, ADC0TH[14:0] are
compared.
Table 57. ADC0TH MMR Bit Designations
Bit Description
15:0 ADC0 16-bit comparator threshold register.
Primary Channel ADC Threshold Counter Limit Register
Name: ADC0THC
Address: 0xFFFF0540
Default value: 0x0001
Access: Read and write
Function: This 8-bit MMR determines how many
cumulative (values below the threshold
decrement or reset the count to 0) primary
ADC conversion result readings above
ADC0TH must occur before the primary
ADC comparator threshold bit is set in the
ADCSTA MMR, generating an ADC
interrupt. The primary ADC comparator
threshold bit is asserted as soon as
ADC0THV = ADC0RCR.
Table 58. ADC0THC MMR Bit Designations
Bit Description
15:8 Reserved.
7:0 ADC0 8-bit threshold counter limit register.
Primary Channel ADC Threshold Counter Register
Name: ADC0THV
Address: 0xFFFF0544
Default value: 0x0000
Access: Read only
Function:
This 8-bit MMR is incremented every time
the absolute value of a primary ADC
conversion result |Result| ≥ ADC0TH. This
register is decremented or reset to 0 every
time the absolute value of a primary ADC
conversion result |Result| < ADC0TH. The
configuration of this function is enabled via
the primary channel ADC comparator bits in
the ADCCFG MMR.
Table 59. ADC0THV MMR Bit Designations
Bit Description
7:0 ADC0 8-bit threshold exceeded counter register.
Primary Channel ADC Accumulator Register
Name: ADC0ACC
Address: 0xFFFF0548
Default value: 0x00000000
Access: Read only
Function:
This 32-bit MMR holds the primary ADC
accumulator value. The primary ADC ready bit
in the ADCSTA MMR should be used to
determine when it is safe to read this MMR.
The MMR value is reset to 0 by disabling the
accumulator in the ADCCFG MMR or by
reconfiguring the primary channel ADC.
Table 60. ADC0ACC MMR Bit Designations
Bit Description
31:0 ADC0 32-bit accumulator register.