Datasheet

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 51 of 108
Table 52. ADC1OF MMR Bit Designations
Bit Description
15:0 ADC1 16-bit offset calibration value.
Primary Channel ADC Gain Calibration Register
Name: ADC0GN
Address: 0xFFFF052C
Default value: Part specific, factory programmed
Access: Read and write
Function:
This gain MMR holds a 16-bit gain
calibration coefficient for scaling the primary
ADC conversion result. The register is
configured at power-on with a factory default
value. However, this register is automatically
overwritten if a gain calibration of the
primary ADC is initiated by the user via bits
in the ADCMDE MMR. User code can write
to this calibration register only if the ADC is
in idle mode. An ADC must be enabled and
in idle mode before being written to any
offset or gain register. The ADC must be in
idle mode for at least 23 μs.
Table 53. ADC0GN MMR Bit Designations
Bits Description
15:0 ADC0 16-bit calibration gain value.
Auxiliary Channel Gain Calibration Register
Name: ADC1GN
Address: 0xFFFF0530
Default value: Part specific, factory programmed
Access: Read and write
Function: This gain MMR holds a 16-bit gain calibra-
tion coefficient for scaling an auxiliary channel
conversion result. The register is configured
at power-on with a factory default value.
However, this register is automatically over-
written if a gain calibration of the auxiliary
channel is initiated by the user via bits in the
ADCMDE MMR. User code can write to this
calibration register only if the ADC is in idle
mode. An ADC must be enabled and in idle
mode before being written to any offset or gain
register. The ADC must be in idle mode for at
least 23 µs.
Table 54. ADC1GN MMR Bit Designations
Bits Description
15:0 ADC1 16-bit gain calibration value.
Primary Channel ADC Result Counter Limit Register
Name: ADC0RCR
Address: 0xFFFF0534
Default value: 0x0001
Access: Read and write
Function:
This 16-bit MMR sets the number of
conversions required before an ADC
interrupt is generated. By default, this
register is set to 0x01. The ADC counter
function must be enabled via the ADC result
counter enable bit in the ADCCFG MMR.
Table 55. ADC0RCR MMR Bit Designations
Bits Description
15:0 ADC0 result counter limit/reload register.
Primary Channel ADC Result Counter Register
Name: ADC0RCV
Address: 0xFFFF0538
Default value: 0x0000
Access: Read only
Function: This 16-bit, read-only MMR holds the
current number of primary ADC conversion
results. It is used in conjunction with
ADC0RCR to mask primary channel ADC
interrupts, generating a lower interrupt rate.
When ADC0RCV = ADC0RCR, the value in
ADC0RCV resets to 0 and recommences
counting. It can also be used in conjunction
with the accumulator (ADC0ACC) to allow
an average calculation to be taken. The
result counter is enabled via ADCCFG[0].
This MMR is also reset to 0 when the
primary ADC is reconfigured, that is, when
the ADC0CON or ADCMDE is written.
Table 56. ADC0RCV MMR Bit Designations
Bits Description
15:0
ADC0 result counter register.