Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 5 of 108
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
V
DD
= 2.5 V ± 5%, VREF+ = 1.2 V, VREF− = GND, f
CORE
= 10.24 MHz driven from an external 32.768 kHz watch crystal or on-chip oscillator, all
specifications T
A
= −40°C to +125°C, unless otherwise noted. Output noise specifications can be found in Table 36 (primary ADC) and
Table 38 (ADC auxiliary channel).
Table 1. ADuC706x Specifications
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ADC SPECIFICATIONS For all ADC specifications,
assume normal operating mode
unless specifically stated
otherwise
Conversion Rate
1
Chop off, ADC normal operating
mode
50 8000 Hz
Chop on, ADC normal operating
mode
4 2600 Hz
Chop on, ADC low power mode 1 650 Hz
Main Channel
No Missing Codes
1
Chop off (f
ADC
≤ 1 kHz) 24 Bits
Chop on (f
ADC
≤ 666 Hz) 24 Bits
Integral Nonlinearity
1, 2
Gain = 4 ±15 ppm of FSR
Offset Error
3, 4
Chop off, offset error is in the
order of the noise for the pro-
grammed gain and update rate
following calibration
−27 ±8 +27 μV
Offset Error
1, 3, 4
Chop on −2.7 ±0.5 +2.7 μV
Offset Error Drift vs.
Temperature
5
Chop off (with gain ≤ 64)
650/PGA_GAIN
nV/°C
Chop on (with gain ≤ 64) 10 nV/°C
Full-Scale Error
1, 6, 7, 8
Normal mode −1 ±0.5 +1 mV
Full-Scale Error
6, 8
Low power mode −2 ±1.0 +2 mV
Gain Drift vs. Temperature
9
5 ppm/°C
PGA Gain Mismatch Error ±0.1 %
Power Supply Rejection
1
Chop on, ADC = 1 V (gain = 1) 65 dB
Chop on, ADC = 7.8 mV (gain =
128)
84.7 113 dB
Chop off, ADC = 1 V (gain = 1)
56
65
dB
Auxiliary Channel
No Missing Codes
1
Chop off (f
ADC
≤ 1 kHz) 24 Bits
Chop on (f
ADC
≤ 666 Hz) 24 Bits
Integral Nonlinearity
1
±15 ppm of FSR
Offset Error
4
Chop off −120 ±30 +100 μV
Offset Error
1, 4
Chop on −1.5 ±0.5 +3.2 μV
Offset Error Drift vs.
Temperature
5
Chop off 200 nV/°C
Chop on 10 nV/°C
Full-Scale Error
1, 6, 7, 8
Normal mode −1 ±0.5 +1 mV
Full-Scale Error
1, 6, 8
Low power mode −2 ±1.0 +2 mV
Gain Drift vs. Temperature
9
3
ppm/°C
Power Supply Rejection
1
Chop on, ADC = 1 V 55 65 dB
Chop off, ADC = 1 V 53 65 dB