Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 48 of 108
Bit Name Description
7 NOTCH2 Sinc3 modify. Set by user to modify the standard sinc3 frequency response to increase the filter stop-band rejection by
approximately 5 dB. This is achieved by inserting a second notch (NOTCH2) at
f
NOTCH2
= 1.333 × f
NOTCH
where f
NOTCH
is the location of the first notch in the response.
6:0 SF[6:0] Sinc3 decimation factor (SF).
1
The value (SF) written in these bits controls the oversampling (decimation factor) of the
sinc3 filter. The output rate from the sinc3 filter is given by
f
ADC
= (512,000/([SF + 1] × 64)) Hz
2
when the chop bit (Bit 15, chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125.
For SF = 126, f
ADC
is forced to 60 Hz.
For SF = 127, f
ADC
is forced to 50 Hz.
For information on calculating the f
ADC
for SF (other than 126 and 127) and AF values, refer to Table 46.
1
Due to limitations on the digital filter internal data path, there are some limitations on the combinations of the sinc3 decimation factor (SF) and averaging factor (AF)
that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in lower power mode.
2
In low power mode, the ADC is driven directly by the low power oscillator (131 kHz) and not 512 kHz. All f
ADC
calculations should be divided by 4 (approximately).
Table 46. ADC Conversion Rates and Settling Times
Chop
Enabled
Averaging
Factor
Running
Average
f
ADC
Normal Mode f
ADC
Low Power Mode t
SETTLING
1
No
No
No
64]1[
000,512
×+SF
64]1[
072,131
×+SF
ADC
f
3
No
No
Yes
64]1[
000,512
×+SF
64]1[
072,131
×+SF
ADC
f
4
No Yes No
]3[64]1[
000,512
AFSF +××+
]3[64]1[
072,131
AFSF +××+
ADC
f
1
No Yes Yes
]3[64]1[
000,512
AFSF +××+
]3[64]1[
072,131
AFSF +××+
ADC
f
2
Yes N/A N/A
3]3[64]1[
000,512
++××+ AFSF
3]3[64]1[
072,131
++××+ AFSF
ADC
f
2
1
An additional time of approximately 60 µs per ADC is required before the first ADC is available.
Table 47. Allowable Combinations of SF and AF
AF Range
SF
0
1 to 7
8 to 63
0 to 31
Yes
Yes
Yes
32 to 63
Yes
Yes
No
64 to 127 Yes No No