Datasheet

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 35 of 108
By writing to POWCON1, it is possible to further reduce power
consumption in active mode by powering down the UART, PWM
or I
2
C/SPI blocks. To access POWCON1, POWKEY3 must be set to
0x76 in the instruction immediately before accessing POWCON1
and POWKEY4 must be set to 0xB1 in the instruction immediately
after.
For example, the following code enables the SPI/I
2
C blocks but,
powers down the PWM and UART blocks.
POWKEY3 =0x76;
POWCON1 =0x4; //0x100 PWM; 0x20
Uart; 0x4 SPI/I2C
POWKEY4 =0xB1;
Power and Clock Control Registers
POWKEY1 Register
Name: POWKEY1
Address: 0xFFFF0404
Default value: 0xXXXX
Access: Write
Function: When writing to POWCON0, the value of 0x01
must be written to this register in the instruction
immediately before writing to POWCON0.
POWCON0 Register
Name: POWCON0
Address: 0xFFFF0408
Default value: 0x7B
Access: Read and write
Function: This register controls the clock divide bits
controlling the CPU clock (HCLK).
Table 31. POWCON0 MMR Bit Designations
Bit Name Description
7 Reserved This bit must always be set to 0.
6 XPD
XTAL power-down.
Cleared by user to power down the external crystal circuitry.
Set by user to enable the external crystal circuitry.
5
PLLPD
PLL power-down. Timer peripherals power down if driven from the PLL output clock. Timers driven from an active clock
source remain in normal power mode.
This bit is cleared to 0 to power down the PLL. The PLL cannot be powered down if either the core or peripherals are
enabled; Bit 3, Bit 4, and Bit 5 must be cleared simultaneously.
Set by default, and set by hardware on a wake-up event.
4
PPD
Peripherals power-down. The peripherals that are powered down by this bit are as follows:
SRAM, Flash/EE memory and GPIO interfaces, and SPI/I
2
C and UART serial ports.
Cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled; Bit 3 and Bit 4
must be cleared simultaneously.
Set by default and/or by hardware on a wake-up event. Wake-up timer (Timer1) can remain active.
3 COREPD Core power-down. If user code powers down the MCU, include a dummy MCU cycle after the power-down command is
written to POWCON0.
Cleared to power down the ARM core.
Set by default and set by hardware on a wake-up event.
2:0
CD[2:0]
Core clock depends on CD setting:
[000] = 10.24 MHz
[001] = 5.12 MHz
[010] = 2.56 MHz
[011] = 1.28 MHz [default value]
[100] = 640 kHz
[101] = 320 kHz
[110] = 160 kHz
[111] = 80 kHz