Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 30 of 108
Table 21. ADC Address Base = 0xFFFF0500
Address Name Bytes
Access
Type
Default Value Description
0x0500 ADCSTA 2 R 0x0000 ADC status MMR.
0x0504 ADCMSKI 2 R/W 0x0000 ADC interrupt source enable MMR.
0x0508 ADCMDE 1 R/W 0x03 ADC mode register.
0x050C ADC0CON 2 R/W 0x8000 Primary ADC control MMR.
0x0510 ADC1CON 2 R/W 0x0000 Auxiliary ADC control MMR.
0x0514 ADCFLT 2 R/W 0x0007 ADC filter control MMR.
0x0518 ADCCFG 1 R/W 0x00 ADC configuration MMR.
0x051C ADC0DAT 4 R 0x00000000 Primary ADC result MMR.
0x0520 ADC1DAT 4 R 0x00000000 Auxiliary ADC result MMR
0x0524 ADC0OF
1
2 R/W 0x0000, part specific, factory
programmed
Primary ADC offset calibration setting.
0x0528 ADC1OF
1
2 R/W 0x0000, part specific, factory
programmed
Auxiliary ADC offset MMR.
0x052C
ADC0GN
1
2
R/W
0x5555
Primary ADC offset MMR.
0x0530 ADC1GN
1
2 R/W 0x5555 Auxiliary ADC offset MMR. See the ADC operation mode
configuration bit (ADCLPMCFG[1:0]) in Table 42.
0x0534 ADC0RCR 2 R/W 0x0001 Primary ADC result counter/reload MMR.
0x0538 ADC0RCV 2 R 0x0000 Primary ADC result counter MMR.
0x053C ADC0TH 2 R/W 0x0000 Primary ADC 16-bit comparator threshold MMR.
0x0540 ADC0THC 2 R/W 0x0001 Primary ADC 16-bit comparator threshold counter limit.
0x0544 ADC0THV 2 R 0x0000 ADC0 8-bit threshold exceeded counter register
0x0548 ADC0ACC 4 R 0x00000000 Primary ADC accumulator.
0x054C ADC0ATH 4 R/W 0x00000000 Primary ADC 32-bit comparator threshold MMR.
0x0570 IEXCON 1 R/W 0x00 Excitation current sources control register.
1
Updated by the kernel to part specific calibration value.
Table 22. DAC Control Address Base = 0xFFFF0600
Address Name Bytes
Access
Type Default Value Description
0x0600 DAC0CON 2 R/W 0x0200 DAC control register.
0x0604 DAC0DAT 4 R/W 0x00000000 DAC output data register.
Table 23. UART Base Address = 0xFFFF0700
Address Name Bytes
Access
Type Default Value Description
0x0700 COMTX 1 W N/A UART transmit register.
0x0700 COMRX 1 R 0x00 UART receive register.
0x0700 COMDIV0 1 R/W 0x00 UART Standard Baud Rate Generator Divisor Value 0.
0x0704 COMIEN0 1 R/W 0x00 UART Interrupt Enable MMR 0.
0x0704 COMDIV1 1 R/W 0x00 UART Standard Baud Rate Generator Divisor Value 1.
0x0708 COMIID0 1 R 0x01 UART Interrupt Identification 0.
0x070C COMCON0 1 R/W 0x00 UART Control Register 0.
0x0710 COMCON1 1 R/W 0x00 UART Control Register 1.
0x0714 COMSTA0 1 R 0x60 UART Status Register 0.
0x0718
COMSTA1
1
R
0x00
UART Status Register 1.
0X072C COMDIV2 2 R/W 0x0000 UART fractional divider MMR.