Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 3 of 108
REVISION HISTORY
4/12—Rev. C to Rev. D
Changes to Table 1 ............................................................................ 6
Changes to Table 7 .......................................................................... 14
Changes to Table 16 ........................................................................ 25
Change to Command Sequence for Executing a Mass Erase
Section .............................................................................................. 26
Changes to Table 19 ........................................................................ 29
Changes to Power and Clock Control Registers Section ........... 35
Changes to Figure 20 ...................................................................... 55
Changes to Bit 5 in Table 63 ........................................................... 57
Changes to Timers Section; Added Hr:Min:Sec: 1/128 Format
Section and Table 79, Renumbered Sequenitially ....................... 67
Changes to Timer1 or Wake-Up Timer Section ......................... 70
Changes to Timer2 Load Register Section and Timer2 Value
Register Section ............................................................................... 71
Added Table 108 .............................................................................. 98
Updated Outline Dimensions ......................................................105
5/11—Rev. B to Rev. C
Change to Figure 1 ............................................................................ 4
Changes to Table 1 ............................................................................ 6
Add Temporary Protection Section and Keyed Permanent
Protection Section ........................................................................... 25
Added Permanent Protection Section and Sequence to Write
the Software Protection Key and Set Permanent Protection
Section .............................................................................................. 26
Changes to Power Control System Section .................................. 35
Changes to Bit 9:6, Table 43 ........................................................... 45
Changes to Primary Channel ADC Data Register Section and
Table 49 ............................................................................................. 50
Changes to IRQEN Section and IRQCLR Section ..................... 59
Changes to Timer1 or Wake-Up Timer Section ......................... 69
Changes to Table 108 ....................................................................101
2/10—Rev. A to Rev. B
Changes to Features Section ............................................................ 1
Changes to Table 1 ............................................................................ 4
Changes to Digital I/O Voltage to DGND Parameter ................ 14
Changes to Pin 19, Pin 20, and Pin 45 Descriptions (Table 8) .. 16
Changes to Pin 13, Pin 14, and Pin 29 Descriptions (Table 9) .. 18
Changes to Bit 8 in Table 14 ........................................................... 23
Changes to Table 20 ........................................................................ 28
Changes to Power Control System Section .................................. 34
Added Table 32 ................................................................................ 35
Changes to Endnote 2 and Endnote 3 of Table 34 ...................... 36
Changes to Table 42 ........................................................................ 42
Changes to Bit 12 and Bits[3:0] in Table 43 ................................. 44
Changes to Bit 12 in Table 44......................................................... 45
Changes to Endnote 2 in Table 45 ................................................. 47
Changes to Bit 5 in Table 63 ........................................................... 55
Changes to Serial Downloading (In-Circuit Programming)
Section .............................................................................................. 57
Changes to Priority Registers Section .......................................... 61
Changes to GPxPAR Registers Section ......................................101
6/09—Rev. 0 to Rev. A
Added ADuC7061 .............................................................. Universal
Added New Package CP-32-4 ........................................... Universal
Changes to Features Section ............................................................ 1
Changes to General Description Section ....................................... 1
Changes to Figure 1 .......................................................................... 4
Changes to Table 1 ............................................................................ 7
Deleted Endnote to Table 2 ............................................................ 10
Changes to Endnotes, Table 3 and Table 4 ................................... 11
Changes to Endnotes, Table 5 ........................................................ 12
Changes to Endnotes, Table 6 ........................................................ 13
Changes to Figure 7 and Table 8 ................................................... 15
Added Figure 8 and Table 9, Renumbered Sequentially ............ 18
Changes to Flash EE/Control Interface Section .......................... 23
Change to Code 0x04 Description, Table 15 ............................... 24
Change to Bit 31 Description, Table 16 ........................................ 25
Changes to Table 17 ........................................................................ 27
Changes to Table 19 T0CLRI and Table 20 .................................. 28
Changes to Endnote, Table 21 ....................................................... 29
Change to SPITX Default Value, Table 25 ................................... 30
Changes to External Clock Selection Section ............................. 33
Changes to ADC Circuit Information Section............................ 36
Change to Column Heading Table 35 .......................................... 37
Change to Bit 6 Description, Table 39 .......................................... 40
Change to Bit 12 Description, Table 43 ........................................ 44
Changes to Primary Channel ADC Data Register Section
and Auxiliary Channel ADC Data Register Section .................. 48
Change to Table 59 and Figure 17 ................................................. 51
Changes to Using the DAC Section .............................................. 55
Changes to Nonvolatile Flash/EE Memory Section and
Programming Section ..................................................................... 56
Changes to Vectored Interrupt Controller (VIC) Section ......... 59
Changes to Priority Registers Section .......................................... 60
Change to Table 73 .......................................................................... 61
Changes to Figure 23 ...................................................................... 65
Changes Table 78 ............................................................................. 66
Changes to Figure 24 and Table 79 ............................................... 68
Changes to Timer2 Interface Section and Figure 25 ..................
69
Changes to Timer3 Capture Register Section ............................. 71
Change to Bits[16:12] Description, Table 81 ............................... 72
Changes Pulse-Width Modulator General Overview Section,
Table 82, and Figure 26 ................................................................... 73
Changes to Table 84 Column Headings ....................................... 75
Changes to Table 92 ........................................................................ 82
Changes to Bit 1, Table 102 ............................................................ 90
Changes to Bit 11 Description, Table 105 .................................... 95
Changes to SPIMDE Bit Description, Table 106 ......................... 97
Updated Outline Dimensions...................................................... 103
Changes to Ordering Guide ......................................................... 104
4/09—Revision 0: Initial Version