Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions
Data Sheet ADuC7060/ADuC7061
Rev. D | Page 19 of 108
Pin No. Mnemonic Type
1
Description
21 P0.2/MISO/ADC8 I/O General-Purpose Input and General-Purpose Output P0.2/SPI Master Input Slave
Output/Auxiliary ADC8 Input. This is a triple function input/output pin. Single-ended or
differential Analog Input 8. Analog input for the auxiliary ADC.
22 P0.3/MOSI/SDA/ADC9 I/O General-Purpose Input and General-Purpose Output P0.3/SPI Master Output Slave Input/I
2
C
Data Pin/Auxiliary ADC9 Input. This is a multifunction input/output pin. Single-ended or
differential Analog Input 9. Analog input for the auxiliary ADC.
23 XTALO O External Crystal Oscillator Output Pin.
24 XTALI I External Crystal Oscillator Input Pin.
25 P0.4/IRQ0/PWM1 I/O General-Purpose Input and General-Purpose Output P0.4/External Interrupt Request 0/PWM1
Output. This is a triple function input/output pin.
26 P2.0/IRQ2/PWM0 I/O General-Purpose Input and General-Purpose Output P2.0/External Interrupt Request 2/PWM0
Output. This is a triple function input/output pin.
27 DGND S Digital Ground.
28 DVDD S Digital Supply Pin.
29 NTRST/
BM
I JTAG Reset/Boot Mode. Input pin used for debug and download only and boot mode (
BM
). The
ADuC7061 enters serial download mode if
BM
is low at reset and executes code if
BM
is pulled
high at reset through a 13 kΩ resistor.
30 TDO O JTAG Data Out. Output pin used for debug and download only.
31 TDI I JTAG Data In. Input pin used for debug and download only. Add an external pull-up resistor
(~100 kΩ) to this pin.
32 TCK I JTAG Clock. Input pin used for debug and download only. Add an external pull-up resistor
(~100 kΩ) to this pin.
1
I = input, O = output, I/O = input/output, and S = supply.