Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions
Data Sheet ADuC7060/ADuC7061
Rev. D | Page 15 of 108
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TCK
TDI
TDO
DVDD
DGND
P2.1/IRQ3/PWM5
P1.6/PWM4
P1.5/PWM3
P1.4/PWM2
P2.0/IRQ2/PWM0/EXTCLK
P0.4/IRQ0/PWM1
XTALO
P0.3/MOSI/SDA
P0.2/MISO
DVDD
P0.0/SS
P0.1/SCLK/SCL
XTALI
DGND
ADC9
ADC8
ADC6
ADC7
TMS
P1.0/IRQ1/SIN/T0
P1.1/SOUT
P0.5/CTS
P1.3/TRIP
P1.2/SYNC
P0.6/RTS
DVDD
DGND
ADC5/EXT_REF2IN−
DAC0
ADC4/EXT_REF2IN+
ADC3
ADC2
IEXC1
IEXC0
GND_SW
ADC1
ADC0
VREF+
VREF−
AGND
AVDD
RESET
07079-002
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
35
36
34
33
32
31
30
29
28
27
26
25
ADuC7060
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
NOTES
1. THE LFCSP_VQ ONLY HAS AN EXPOSED PADDLE THAT MUST BE LEFT UNCONNECTED.
THIS DOES NOT APPLY TO THE LQFP.
NTRST/BM
Figure 7. 48-Lead LQFP and 48-Lead LFCSP_VQ Pin Configuration
Table 8. ADuC7060 Pin Function Descriptions
Pin
No. Mnemonic Type
1
Description
0 EP Exposed Paddle. The LFCSP_VQ only has an exposed paddle that must be left unconnected.
This does not apply to the LQFP.
1
RESET
I Reset. Input pin, active low. An external 1 kΩ pull-up resistor is recommended with this pin.
2 TMS I JTAG Test Mode Select. Input pin used for debug and download. An external pull-up resistor
(~100 kΩ) should be added to this pin.
3 P1.0/IRQ1/SIN/T0 I/O General-Purpose Input and General Purpose Output P1.0/External Interrupt Request 1/Serial
Input/Timer0 Input. This is a multifunction input/output pin offering four functions.
4 P1.1/SOUT I/O General-Purpose Input and General-Purpose Output P1.1/Serial Output. This is a dual function
input/output pin.
5 P1.2/SYNC I/O General-Purpose Input and General-Purpose Output P1.2/PWM External Sync Input. This is a
dual function input/output pin.
6 P1.3/TRIP I/O General-Purpose Input and General-Purpose Output P1.3/PWM External Trip Input. This is a
dual function input/output pin.
7 P0.5/CTS I/O General-Purpose Input and General-Purpose Output P0.5/Clear-to-Send Signal in UART Mode.
8 P0.6/RTS I/O General-Purpose Input and General-Purpose Output P0.6/Request-to-Send Signal in UART Mode.
9 DVDD S Digital Supply Pin.
10 DGND S Digital Ground.
11 DAC0 O DAC Output. Analog output pin.