Datasheet

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 12 of 108
07079-031
SCLOCK
(POLARITY = 0)
SCLOCK
(POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
MOSI MSB BITS 6 TO 1 LSB
MISO MSB IN BITS 6 TO 1 LSB IN
t
DR
t
DF
t
DAV
t
DOSU
t
DSU
t
DHD
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
Table 5. SPI Slave Mode Timing (Phase Mode = 1)
Parameter Description Min Typ Max Unit
t
CS
E
CS
E
to SCLOCK edge
1
(2 × t
HCLK
) + (2 × t
UCLK
) ns
t
SL
SCLOCK low pulse width (SPIDIV + 1) × t
HCLK
ns
t
SH
SCLOCK high pulse width (SPIDIV + 1) × t
HCLK
ns
t
DAV
Data output valid after SCLOCK edge 40 ns
t
DSU
Data input setup time before SCLOCK edge
1
1 × t
UCLK
ns
t
DHD
Data input hold time after SCLOCK edge
1
2 × t
UCLK
ns
t
DF
Data output fall time 30 40 ns
t
DR
Data output rise time 30 40 ns
t
SR
SCLOCK rise time 1 ns
t
SF
SCLOCK fall time 1 ns
t
SFS
CS
E
high after SCLOCK edge
0 ns
1
t
UCLK
= 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL.
07079-032
SCLOCK
(POLARITY = 0)
CS
SCLOCK
(POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
t
SFS
MISO MSB BITS 6 TO 1 LSB
MOSI MSB IN BITS 6 TO 1 LSB IN
t
DHD
t
DSU
t
DAV
t
DR
t
DF
t
CS
Figure 5. SPI Slave Mode Timing (Phase Mode = 1)