Datasheet

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 11 of 108
SPI Timing
Table 3. SPI Master Mode Timing (Phase Mode = 1)
Parameter Description Min Typ Max Unit
t
SL
SCLOCK low pulse width (SPIDIV + 1) × t
HCLK
ns
t
SH
SCLOCK high pulse width (SPIDIV + 1) × t
HCLK
ns
t
DAV
Data output valid after SCLOCK edge 25 ns
t
DSU
Data input setup time before SCLOCK edge
1
1 × t
UCLK
ns
t
DHD
Data input hold time after SCLOCK edge
1
2 × t
UCLK
ns
t
DF
Data output fall time 30 40 ns
t
DR
Data output rise time 30 40 ns
t
SR
SCLOCK rise time 30 40 ns
t
SF
SCLOCK fall time 30 40 ns
1
t
UCLK
= 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL.
0
7079-030
SCLOCK
(POLARITY = 0)
SCLOCK
(POLARITY = 1)
MOSI MSB BITS 6 TO 1 LSB
MISO MSB IN BITS 6 TO 1 LSB IN
t
SH
t
SL
t
SR
t
SF
t
DR
t
DF
t
DAV
t
DSU
t
DHD
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
Table 4. SPI Master Mode Timing (Phase Mode = 0)
Parameter Description Min Typ Max Unit
t
SL
SCLOCK low pulse width (SPIDIV + 1) × t
HCLK
ns
t
SH
SCLOCK high pulse width (SPIDIV + 1) × t
HCLK
ns
t
DAV
Data output valid after SCLOCK edge 25 ns
t
DOSU
Data output setup before SCLOCK edge 90 ns
t
DSU
Data input setup time before SCLOCK edge
1
1 × t
UCLK
ns
t
DHD
Data input hold time after SCLOCK edge
1
2 × t
UCLK
ns
t
DF
Data output fall time 30 40 ns
t
DR
Data output rise time 30 40 ns
t
SR
SCLOCK rise time 30 40 ns
t
SF
SCLOCK fall time 30 40 ns
1
t
UCLK
= 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL.