Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 90 of 108
I
2
C Master Receive, I2CMRX, Register
Name: I2CMRX
Address: 0xFFFF0908
Default value: 0x00
Access: Read only
Function: This 8-bit MMR is the I
2
C master receive
register.
I
2
C Master Transmit, I2CMTX, Register
Name: I2CMTX
Address: 0xFFFF090C
Default value: 0x00
Access: Write only
Function: This 8-bit MMR is the I
2
C master transmit
register.
I
2
C Master Read Count, I2CMCNT0, Register
Name: I2CMCNT0
Address: 0xFFFF0910
Default value: 0x0000
Access: Read and write
Function: This 16-bit MMR holds the required number
of bytes when the master begins a read
sequence from a slave device.
Table 99. I2CMCNT0 MMR Bit Designations
Bit Name Description
15:9 Reserved.
8 I2CRECNT Set this bit if more than 256 bytes are
required from the slave.
Clear this bit when reading 256 bytes or
fewer.
7:0 I2CRCNT These eight bits hold the number of bytes
required during a slave read sequence,
minus 1. If only a single byte is required, set
these bits to 0.
I
2
C Master Current Read Count, I2CMCNT1, Register
Name: I2CMCNT1
Address: 0xFFFF0914
Default value: 0x00
Access: Read only
Function: This 8-bit MMR holds the number of bytes
received so far during a read sequence with a
slave device.
I
2
C Address 0, I2CADR0, Register
Name: I2CADR0
Address: 0xFFFF0918
Default value: 0x00
Access: Read and write
Function: This 8-bit MMR holds the 7-bit slave address
and the read/write bit when the master begins
communicating with a slave.
Table 100. I2CADR0 MMR in 7-Bit Address Mode
Bit Name Description
7:1 I2CADR These bits contain the 7-bit address of the
required slave device.
0 R/
W
Bit 0 is the read/write bit.
When this bit = 1, a read sequence is requested.
When this bit = 0, a write sequence is requested.
Table 101. I2CADR0 MMR in 10-Bit Address Mode
Bit Name Description
7:3 These bits must be set to [11110b] in 10-bit
address mode.
2:1
I2CMADR
These bits contain ADDR[9:8] in 10-bit
addressing mode.
0 R/
W
Read/write bit.
When this bit = 1, a read sequence is
requested.
When this bit = 0, a write sequence is
requested.