Datasheet

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 9 of 108
Parameter Test Conditions/Comments Min Typ Max Unit
POWER REQUIREMENTS
Power Supply Voltages
DVDD (±5%) 2.375 2.5 2.625 V
AVDD (±5%) 2.375 2.5 2.625 V
Power Consumption
I
DD
(MCU Normal Mode)
18
MCU clock rate = 10.24 MHz,
ADC0 on
6 10 mA
MCU clock rate = 640 kHz,
ADC0 on, G = 4, ADC1/DAC off,
SPI on; POWCON1 = 0x4
Full temperature range 3.1 mA
Reduced temperature range
−40°C to +85°C
1
2.74 mA
I
DD
(MCU Powered Down)
1
Full temperature range 55 350 µA
Reduced temperature range
−40°C to +85°C
55 120 µA
I
DD
(Primary ADC) PGA enabled, normal mode/low
power mode; current is
dependent on gain setting
0.6/0.3 mA
ADC0 on, G = 1, normal mode 0.03 mA
ADC0 on, G = 4, normal mode 0.44 mA
ADC0 on, G = >128, normal mode 0.63 mA
I
DD
(Auxiliary ADC) Normal mode/low power mode 0.35/0.1 mA
I
DD
(DAC) DAC0CON = 0x10 0.33 mA
PWM 0.34 mA
1
These numbers are not production tested but are guaranteed by design and/or characterization data at production release.
2
Valid for primary ADC gain setting of PGA = 4 to 64.
3
Tested at gain range = 4 after initial offset calibration.
4
Measured with an internal short. A system zero-scale calibration removes this error.
5
Measured with an internal short.
6
These numbers do not include internal reference temperature drift.
7
Factory calibrated at gain = 1.
8
System calibration at a specific gain range removes the error at this gain range.
9
Measured using an external reference.
10
Ensure common mode voltage is set so VIN*Gain setting, which is the PGA output voltage, is between 0.1V and VDD – 0.7V. 900 mV is an optimum value for the
common mode voltage across all gains.
11
Measured using the box method.
12
References up to AVDD are accommodated by setting ADC0CON Bit 12.
13
Reference DAC linearity is calculated using a reduced code range of 171 to 4095.
14
Reference DAC linearity is calculated using a reduced code range of 2731 to 65,535.
15
Die temperature.
16
Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
17
Retention lifetime equivalent at junction temperature (T
J
) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
18
Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.