Datasheet

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 88 of 108
Table 97. I2CMCON MMR Bit Designations
Bit Name Description
15:9 Reserved. These bits are reserved and should not be written to.
8
I2CMCENI
I
2
C transmission complete interrupt enable bit.
Set this bit to enable an interrupt on detecting a stop condition on the I
2
C bus.
Clear this interrupt source.
7 I2CNACKENI I
2
C no acknowledge (NACK) received interrupt enable bit.
Set this bit to enable interrupts when the I
2
C master receives a no acknowledge.
Clear this interrupt source.
6 I2CALENI I
2
C arbitration lost interrupt enable bit.
Set this bit to enable interrupts when the I
2
C master did not gain control of the I
2
C bus.
Clear this interrupt source.
5 I2CMTENI I
2
C transmit interrupt enable bit.
Set this bit to enable interrupts when the I
2
C master has transmitted a byte.
Clear this interrupt source.
4 I2CMRENI I
2
C receive interrupt enable bit.
Set this bit to enable interrupts when the I
2
C master receives data.
Cleared by user to disable interrupts when the I
2
C master is receiving data.
3 I2CMSEN I
2
C master SCL stretch enable bit.
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until
I2CMSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.
Clear this bit to disable clock stretching.
2 I2CILEN I
2
C internal loopback enable.
Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their
respective input signals.
Cleared by user to disable loopback mode.
1 I2CBD I
2
C master backoff disable bit.
Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start
condition.
Clear this bit to back off until the I
2
C bus becomes free.
0
I2CMEN
I
2
C master enable bit.
Set by user to enable the I
2
C master mode.
Cleared to disable the I
2
C master mode.