Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 84 of 108
UART Status Register 1
COMSTA1 Register
Name: COMSTA1
Address: 0xFFFF0718
Default value: 0x00
Access: Read only
Function: COMSTA1 is a modem status register.
Table 93. COMSTA1 MMR Bit Designations
Bit Name Description
7:5 Reserved. Not used.
4 CTS Clear to send.
3:1 Reserved. Not used.
0 DCTS Delta CTS.
Set automatically if CTS changed state since
COMSTA1 was last read.
Cleared automatically by reading COMSTA1.
UART Interrupt Enable Register 0
COMIEN0 Register
Name: COMIEN0
Address: 0xFFFF0704
Default value: 0x00
Access: Read and write
Function: This 8-bit register enables and disables the
individual UART interrupt sources.
Table 94. COMIEN0 MMR Bit Designations
Bit Name Description
7:4 Reserved. Not used.
3 EDSSI Modem status interrupt enable bit.
Set by user to enable generation of an
interrupt if any of COMSTA0[3:1] are set.
Cleared by user.
2 ELSI Receive status interrupt enable bit.
Set by user to enable generation of an
interrupt if any of the COMSTA0[3:1] register
bits are set.
Cleared by user.
1 ETBEI Enable transmit buffer empty interrupt.
Set by user to enable an interrupt when the
buffer is empty during a transmission; that is,
when COMSTA0[5] is set.
Cleared by user.
0 ERBFI Enable receive buffer full interrupt.
Set by user to enable an interrupt when the
buffer is full during a reception.
Cleared by user.
UART Interrupt Identification Register 0
COMIID0 Register
Name: COMIID0
Address: 0xFFFF0708
Default value: 0x01
Access: Read only
Function: This 8-bit register reflects the source of the
UART interrupt.