Datasheet

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 75 of 108
PULSE-WIDTH MODULATOR
PULSE-WIDTH MODULATOR GENERAL OVERVIEW
Each ADuC706x integrates a 6-channel pulse-width modulator
(PWM) interface. The PWM outputs can be configured to drive
an H-bridge or can be used as standard PWM outputs. On
power-up, the PWM outputs default to H-bridge mode. This
ensures that the motor is turned off by default. In standard
PWM mode, the outputs are arranged as three pairs of PWM
pins. Users have control over the period of each pair of outputs
and over the duty cycle of each individual output.
Table 84. PWM MMRs
MMR Name Description
PWMCON PWM control.
PWM0COM0 Compare Register 0 for PWM Output 0 and
PWM Output 1.
PWM0COM1
Compare Register 1 for PWM Output 0 and
PWM Output 1.
PWM0COM2 Compare Register 2 for PWM Output 0 and
PWM Output 1.
PWM0LEN Frequency control for PWM Output 0 and PWM
Output 1.
PWM1COM0 Compare Register 0 for PWM Output 2 and
PWM Output 3.
PWM1COM1 Compare Register 1 for PWM Output 2 and
PWM Output 3.
PWM1COM2 Compare Register 2 for PWM Output 2 and
PWM Output 3.
PWM1LEN Frequency control for PWM Output 2 and PWM
Output 3.
PWM2COM0 Compare Register 0 for PWM Output 4 and
PWM Output 5.
PWM2COM1 Compare Register 1 for PWM Output 4 and
PWM Output 5.
PWM2COM2 Compare Register 2 for PWM Output 4 and
PWM Output 5.
PWM2LEN Frequency control for PWM Output 4 and PWM
Output 5.
PWMCLRI PWM interrupt clear.
In all modes, the PWMxCOMx MMRs control the point at
which the PWM outputs change state. An example of the first
pair of PWM outputs (PWM0 and PWM1) is shown in Figure 26.
HIGH SIDE
(PWM0)
LOW SIDE
(PWM1)
PWM0COM2
PWM0COM1
PWM0COM0
PWM0LEN
07079-020
Figure 26. PWM Timing
The PWM clock is selectable via PWMCON with one of the
following values: UCLK divided by 2, 4, 8, 16, 32, 64, 128, or
256. The length of a PWM period is defined by PWMxLEN.
The PWM waveforms are set by the count value of the 16-bit
timer and the compare registers contents, as shown with the
PWM0 and PWM1 waveforms in Figure 26.
The low-side waveform, PWM1, goes high when the timer
count reaches PWM0LEN, and it goes low when the timer
count reaches the value held in PWM0COM2 or when the
high-side waveform (PWM0) goes low.
The high-side waveform, PWM0, goes high when the timer
count reaches the value held in PWM0COM0, and it goes low
when the timer count reaches the value held in PWM0COM1.
PWMCON Control Register
Name: PWMCON
Address: 0xFFFF0F80
Default value: 0x0012
Access: Read and write
Function: This is a 16-bit MMR that configures the
PWM outputs.