Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 69 of 108
Bit Name Description
5:4 T0FORMAT Format.
[00] = binary (default).
[01] = reserved.
[10] = hours:minutes:seconds:hundredths (23 hours to 0 hours).
[11] = hours:minutes:seconds:hundredths (255 hours to 0 hours).
3:0 T0SCALE Prescaler.
[0000] = source clock/1 (default).
[0100] = source clock/16.
[1000] = source clock/256.
[1111] = source clock/32,768. Note that all other values are undefined.
TIMER1 OR WAKE-UP TIMER
Timer1 is a 32-bit wake-up timer, count down or count up, with
a programmable prescaler. The prescaler is clocked directly from
one of four clock sources, namely, the core clock (which is the
default selection), external 32.768 kHz watch crystal, or the
32.768 kHz oscillator. The selected clock source can be scaled
by a factor of 1, 16, 256, or 32,768. The wake-up timer
continues to run when the core clock is disabled. This gives a
minimum resolution of 97.66 ns when operating at CD zero, the
core is operating at 10.24 MHz, and with a prescaler of 1
(ignoring the external GPIOs).
The counter can be formatted as a plain 32-bit value or as
hours:minutes:seconds:hundredths.
Timer1 reloads the value from T1LD either when Timer1
overflows or immediately when T1LD is written.
The Timer1 interface consists of four MMRS.
• T1LD and T1VAL are 32-bit registers and hold 32-bit,
unsigned integers. T1VAL is read only.
• T1CLRI is an 8-bit register. Writing any value to this
register clears the Timer1 interrupt.
• T1CON is the configuration MMR, described in Table 81.
Timer1 Load Registers
Name: T1LD
Address: 0xFFFF0340
Default value: 0x00000000
Access: Read and write
Function: T1LD is a 32-bit register that holds the 32-bit
value that is loaded into the counter.
Timer1 Clear Register
Name: T1CLRI
Address: 0xFFFF034C
Access: Write only
Function: This 8-bit, write-only MMR is written (with
any value) by user code to clear the interrupt.
Timer1 Value Register
Name: T1VA L
Address: 0xFFFF0344
Default value: 0xFFFFFFFF
Access: Read only
Function: T1VAL is a 32-bit register that holds the
current value of Timer1.