Datasheet

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 68 of 108
Timer0 Capture Register
Name: T0CAP
Address: 0xFFFF0330
Default value: 0x00000000
Access: Read only
Function: This 32-bit register holds the 32-bit value captured by an enabled IRQ event.
Timer0 Control Register
Name: T0CON
Address: 0xFFFF0328
Default value: 0x01000000
Access: Read and write
Function: This 32-bit MMR configures the mode of operation of Timer0.
Table 80. T0CON MMR Bit Designations
Bit Name Description
31:24 T0PVAL 8-bit postscaler.
By writing to these eight bits, a value is written to the postscaler. Writing 0 is interpreted as a 1.
By reading these eight bits, the current value of the counter is read.
23 T0PEN Timer0 enable postscaler.
Set to enable the Timer0 postscaler. If enabled, interrupts are generated after T0CON[31:24] periods
as defined by T0LD.
Cleared to disable the Timer0 postscaler.
22:20 Reserved. These bits are reserved and should be written as 0 by user code.
19 T0PCF Postscaler compare flag; read only. Set if the number of Timer0 overflows is equal to the number written
to the postscaler.
18 T0SRCI Timer0 interrupt source.
Set to select interrupt generation from the postscaler counter.
Cleared to select interrupt generation directly from Timer0.
17 T0CAPEN Event enable bit.
Set by user to enable time capture of an event.
Cleared by user to disable time capture of an event.
16:12 T0CAPSEL Event Select Bits[17:0]. The events are described in Table 78.
11
Reserved bit.
10:9 T0CLKSEL Clock select.
[00] = 32.768 kHz.
[01] = 10.24 MHz/CD.
[10] = 10.24 MHz.
[11] = P1.0.
8 T0DIR Count up.
Set by user for Timer0 to count up.
Cleared by user for Timer0 to count down (default).
7 T0EN Timer0 enable bit.
Set by user to enable Timer0.
Cleared by user to disable Timer0 (default).
6 T0MOD Timer0 mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode (default).