Datasheet

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 63 of 108
IRQCONN
The IRQCONN register is the IRQ and FIQ control register. It
contains two active bits: the first to enable nesting and
prioritization of IRQ interrupts, and the other to enable nesting
and prioritization of FIQ interrupts.
If these bits are cleared, FIQs and IRQs can still be used, but it is
not possible to nest IRQs or FIQs. Neither is it possible to set an
interrupt source priority level. In this default state, an FIQ does
have a higher priority than an IRQ.
IRQCONN Register
Name: IRQCONN
Address: 0xFFFF0030
Default value: 0x00000000
Access: Read and write
Table 72. IRQCONN MMR Bit Designations
Bit Name Description
31:2 Reserved These bits are reserved and should not be
written to.
1 ENFIQN Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
0 ENIRQN Setting this bit to 1 enables nesting of IRQ
interrupts. Clearing this bit means no nesting
or prioritization of IRQs is allowed.
IRQSTAN
If IRQCONN[0] is asserted and IRQVEC is read, then one of
these bits is asserted. The bit that asserts depends on the
priority of the IRQ. If the IRQ is of Priority 0, then Bit 0 asserts;
Priority 1, then Bit 1 asserts; and so forth. When a bit is set in
this register, all interrupts of that priority and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is possible to clear only one bit at a time. For
example, if this register is set to 0x09, writing 0xFF changes the
register to 0x08, and writing 0xFF a second time changes the
register to 0x00.
IRQSTAN Register
Name: IRQSTAN
Address: 0xFFFF003C
Default value: 0x00000000
Access: Read and write
Table 73. IRQSTAN MMR Bit Designations
Bit Name Description
31:8 Reserved These bits are reserved and should not be
written to.
7:0 Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
FIQVEC
The FIQ interrupt vector register, FIQVEC, points to a memory
address containing a pointer to the interrupt service routine of
the currently active FIQ. This register should be read only when
an FIQ occurs and FIQ interrupt nesting has been enabled by
setting Bit 1 of the IRQCONN register.
FIQVEC Register
Name: FIQVEC
Address: 0xFFFF011C
Default value: 0x00000000
Access: Read only
Table 74. FIQVEC MMR Bit Designations
Bit Access
Initial
Value
Description
31:23 Read only 0 Always read as 0.
22:7 Read only 0 IRQBASE register value.
6:2 0 Highest priority FIQ source. This is
a value between 0 to 19 that
represents the possible interrupt
sources. For example, if the
highest currently active FIQ is
Timer1, then these bits are
[01000].
1:0 Reserved 0 Reserved bits.