Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 62 of 108
Table 68. IRQVEC MMR Bit Designations
Bit Access
Initial
Value
Description
31:23 Read
only
0 Always read as 0.
22:7 Read
only
0 IRQBASE register value.
6:2 Read
only
0 Highest priority IRQ source. This
is a value between 0 to 19 repre-
senting the possible interrupt
sources. For example, if the highest
currently active IRQ is Timer1, then
these bits are [01000].
1:0
Reserved
0
Reserved bits.
Priority Registers
The interrupt priority registers, IRQP0, IRQP1, and IRQP2,
allow each interrupt source to have its priority level configured
for a level between 0 and 7. Level 0 is the highest priority level.
IRQP0 Register
Name: IRQP0
Address: 0xFFFF0020
Default value: 0x00000000
Access: Read and write
Table 69. IRQP0 MMR Bit Designations
Bit Name Description
31:27 Reserved Reserved bits.
26:24 T3PI A priority level of 0 to 7 can be set for
Timer3.
23 Reserved Reserved bit.
22:20 T2PI A priority level of 0 to 7 can be set for
Timer2.
19 Reserved Reserved bit.
18:16 T1PI A priority level of 0 to 7 can be set for
Timer1.
15 Reserved Reserved bit.
14:12 T0PI A priority level of 0 to 7 can be set for
Timer0.
11:7 Reserved Reserved bits.
6:4
SWINTP
A priority level of 0 to 7 can be set for the
software interrupt source.
3:0 Reserved Interrupt 0 cannot be prioritized.
IRQP1 Register
Name: IRQP1
Address: 0xFFFF0024
Default value: 0x00000000
Access: Read and write
Table 70. IRQP1 MMR Bit Designations
Bit Name Description
31 Reserved Reserved bit.
30:28 I2CMPI A priority level of 0 to 7 can be set for I
2
C
master.
27 Reserved Reserved bit.
26:24 IRQ1PI A priority level of 0 to 7 can be set for IRQ1.
23 Reserved Reserved bit.
22:20 IRQ0PI A priority level of 0 to 7 can be set for IRQ0.
19 Reserved Reserved bit.
18:16 SPIMPI A priority level of 0 to 7 can be set for SPI
master.
15 Reserved Reserved bit.
14:12 UARTPI A priority level of 0 to 7 can be set for UART.
11 Reserved Reserved bit.
10:8 ADCPI A priority level of 0 to 7 can be set for the
ADC interrupt source.
7:0 Reserved Reserved bits.
IRQP2 Register
Name: IRQP2
Address: 0xFFFF0028
Default value: 0x00000000
Access: Read and write
Table 71. IRQP2 MMR Bit Designations
Bit
Name
Description
31:15 Reserved Reserved bit.
14:12 IRQ3PI A priority level of 0 to 7 can be set for IRQ3.
11 Reserved Reserved bit.
10:8 IRQ2PI A priority level of 0 to 7 can be set for IRQ2.
7 Reserved Reserved bit.
6:4 SPISPI A priority level of 0 to 7 can be set for SPI
slave.
3
Reserved
Reserved bit.
2:0 I2CSPI A priority level of 0 to 7 can be set for I
2
C
slave.