Datasheet

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 56 of 108
DAC PERIPHERALS
DAC
The ADuC706x incorporates a voltage output DAC on chip. In
normal mode, the DAC resolution is 12-bits. In interpolation,
the DAC resolution is 16 bits with 14 effective bits. The DAC
has a rail-to-rail voltage output buffer capable of driving
5 kΩ/100 pF.
The DAC has four selectable ranges.
• 0 V to V
REF
(internal band gap 1.2 V reference)
• VREF− to VREF+
• ADC5/EXT_REF2IN− to ADC4/EXT_REF2IN+
• 0 V to AVDD
The maximum signal range is 0 V to AVDD.
Op Amp Mode
As an option, the DAC can be disabled and its output buffer
used as an op amp.
MMR INTERFACE
The DAC is configurable through a control register and a data
register.
DAC0CON Register
Name: DAC0CON
Address: 0xFFFF0600
Default value: 0x0200
Access: Read and write
Table 63. DAC0CON MMR Bit Designations
Bit Name Description
15:10 Reserved.
9 DACPD Set to 1 to power down DAC output (DAC output is tristated).
Clear this bit to enable the DAC.
8 DACBUFLP Set to 1 to place the DAC output buffer in low power mode. See the Normal DAC Mode and Op Amp Mode
sections for further details on electrical specifications.
Clear this bit to enable the DAC buffer.
7 OPAMP Set to 1 to place the DAC output buffer in op amp mode.
Clear this bit to enable the DAC output buffer for normal DAC operation.
6 DACBUFBYPASS Set to 1 to bypass the output buffer and send the DAC output directly to the output pin.
Clear this bit to buffer the DAC output.
5 DACCLK Cleared to 0 to update the DAC on the negative edge of HCLK.
Set to 1 to update the DAC on the negative edge of Timer0. This mode is ideally suited for waveform generation
where the next value in the waveform is written to DAC0DAT at regular intervals of Timer0.
4
DACCLR
Set to 1 for normal DAC operation.
Set to 0
to clear the DAC output and to set DAC0DAT to 0. Writing to this bit has an immediate effect on the DAC
output.
3 DACMODE Set to 1 to enable the DAC in 16-bit interpolation mode.
Set to 0 to enable the DAC in normal 12-bit mode.
2 Rate Used with interpolation mode.
Set to 1 to configure the interpolation clock as UCLK/16.
Set to 0 to configure the interpolation clock as UCLK/32.
1:0 DAC range bits [11] = 0 V to AVDD range.
[10] = ADC5/EXT_REF2IN− to ADC4/EXT_REF2IN+.
[01] = VREF− to VREF+.
[00] = 0 V to V
REF
(1.2 V) range. Internal reference source.