Datasheet

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 34 of 108
OSCILLATOR, PLL, AND POWER CONTROL
CLOCKING SYSTEM
The ADuC706x integrates a 32.768 kHz ±3% oscillator, a clock
divider, and a PLL. The PLL locks onto a multiple of the inter-
nal oscillator or an external 32.768 kHz crystal to provide a stable
10.24 MHz clock (UCLK) for the system. To allow power saving,
the core can operate at this frequency or at binary submultiples
of it. The actual core operating frequency, UCLK/2
CD
, is refered
to as HCLK. The default core clock is the PLL clock divided by 8
(CD = 3) or 1.28 MHz.
PLL
CORE
CD
10.24MHz
32.768kHz
*32.768kHz ± 3%
HCLK
UCLK
OCLK
WATCHDOG
TIMER
WAKE-UP
TIMER
INT. 32kHz
OSCILLATOR*
CRYSTAL
OSCILLATOR
XCLKO
XCLKI
ANALOG
PERIPHERALS
/2
CD
I
2
C
07079-008
P2.0/EXTCLK
Figure 13. Clocking System
External Crystal Selection
To switch to an external crystal, users must follow this procedure:
1. Enable the Timer1 interrupt and configure it for a timeout
period of >120 µs.
2. Follow the write sequence to the PLLCON register, setting the
OSEL bits to [10] and clearing the EXTCLK bit.
3. Force the part into nap mode by following the correct write
sequence to the POWCON register.
4. When the part is interrupted from nap mode by the Timer1
interrupt source, the clock source has switched to the external
crystal.
Example source code
T1LD = 0x80; // 32,768 clock ticks
T1CON = 0xC0; // Periodic mode, enable
// timer, 32,768 Hz clock/1
IRQEN |= 0x10; // Enable Timer1 interrupt
// source
PLLKEY1 = 0xAA; // Switch to external crystal
PLLCON = 0x2;
PLLKEY2 = 0x55;
POWKEY1 = 0x1; // Enter nap mode
POWCON0 = 0x73;
POWKEY2 = 0xF4;
In case of crystal loss, the watchdog timer should be used. During
initialization, a test on the RSTSTA can determine if the reset came
from the watchdog timer.
External Clock Selection
To switch to an external clock on P2.0, configure P2.0 in Mode 0.
The external clock can be up to 20.48 MHz, provided that the toler-
ance is 1%. The external clock is divided by 2 internally on the part.
Example source code
T1LD = 0x80;
T1CON = 0xC0;
IRQEN |= 0x10; // Enable Timer1 interrupt
PLLKEY1 = 0xAA; // Switch to external clock
PLLCON = 0x4;
PLLKEY2 = 0x55;
POWKEY1 = 0x1; // Enter NAP mode
POWCON0 = 0x73;
POWKEY2 = 0xF4;
The selection of the clock source is in the PLLCON register. By
default, the part uses the internal oscillator feeding the PLL.
POWER CONTROL SYSTEM
The core clock frequency is changed by writing to the POWCON0
register. This is a key protected register; therefore, Register POWKEY1
and Register POWKEY2 must be written to immediately before and
after configuring the POWCON0 register. The following is a simple
example showing how to configure the core clock for 10.24 MHz:
POWKEY1 = 0x1;
POWCON0 = 0x78; //Set core to max CPU
//speed of 10.24 MHz
POWKEY2 = 0xF4;
A choice of operating modes is available on the ADuC706x. Table 33
describes what part is powered on in the different modes and
indicates the power-up time.
Table 34 gives some typical values for the total current consumption
(analog + digital supply currents) in the different modes, depending
on the clock divider bits. The ADC is turned off. Note that these
values also include the current consumption of the regulator and
other parts on the test board where these values are measured.