Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 33 of 108
RESET
There are four kinds of resets: external reset, power-on reset,
watchdog reset, and software reset. The RSTSTA register
indicates the source of the last reset and can be written by user
code to initiate a software reset event.
The bits in this register can be cleared to 0 by writing to the
RSTCLR MMR at 0xFFFF0234. The bit designations in
RSTCLR mirror those of RSTSTA. These registers can be used
during a reset exception service routine to identify the source of
the reset. The implications of all four kinds of reset events are
tabulated in Table 30.
RSTSTA Register
Name: RSTSTA
Address: 0xFFFF0230
Default value: Depends on type of reset
Access: Read and write
Function: This 8-bit register indicates the source of the
last reset event and can be written by user code
to initiate a software reset.
RSTCLR Register
Name: RSTCLR
Address: 0xFFFF0234
Access: Write only
Function: This 8-bit write only register clears the corres-
ponding bit in RSTSTA.
Table 29. RSTSTA/RSTCLR MMR Bit Designations
Bit Description
7:4 Not used. These bits are not used and always
read as 0.
3 External reset.
Automatically set to 1 when an external reset
occurs.
This bit is cleared by setting the corresponding bit
in RSTCLR.
2 Software reset.
This bit is set to 1 by user code to generate a soft-
ware reset.
This bit is cleared by setting the corresponding bit
in RSTCLR.
1
1 Watchdog timeout.
Automatically set to 1 when a watchdog timeout
occurs.
Cleared by setting the corresponding bit in RSTCLR.
0 Power-on reset.
Automatically set when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
1
If the software reset bit in RSTSTA is set, any write to RSTCLR that does not
clear this bit generates a software reset.
Table 30. Device Reset Implications
RESET
Reset
External Pins to
Default State
Kernel
Executed
Reset All
External MMRs
(Excluding RSTSTA)
Peripherals
Reset
Watchdog
Timer Reset
RAM
Valid
RSTSTA
(Status After
Reset Event)
POR Yes Yes Yes Yes Yes Yes/No RSTSTA[0] = 1
Watchdog Yes Yes Yes Yes No Yes RSTSTA[1] = 1
Software Yes Yes Yes Yes No Yes RSTSTA[2] = 1
External Pin Yes Yes Yes Yes No Yes RSTSTA[3] = 1