Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 28 of 108
COMPLETE MMR LISTING
In the following MMR tables, addresses are listed in hexadecimal code. Access types include R for read, W for write, and R/W for read
and write.
Table 17. IRQ Address Base = 0xFFFF0000
Address Name Bytes
Access
Type Default Value Description
0x0000 IRQSTA 4 R 0x00000000 Active IRQ source status.
0x0004 IRQSIG 4 R Current state of all IRQ sources (enabled and disabled).
0x0008 IRQEN 4 R/W 0x00000000 Enabled IRQ sources.
0x000C IRQCLR 4 W 0x00000000 MMR to disable IRQ sources.
0x0010 SWICFG 4 W 0x00000000 Software interrupt configuration MMR.
0x0014 IRQBASE 4 R/W 0x00000000 Base address of all vectors. Points to the start of the 64-byte memory block,
which can contain up to 32 pointers to separate subroutine handlers.
0x001C IRQVEC 4 R 0x00000000 This register contains the subroutine address for the currently active
IRQ source.
0x0020 IRQP0 4 R/W 0x00000000 Contains the interrupt priority setting for Interrupt Source 1 to Interrupt
Source 7. An interrupt can have a priority setting of 0 to 7.
0x0024 IRQP1 4 R/W 0x00000000 Contains the interrupt priority setting for Interrupt Source 8 to Interrupt
Source 15.
0x0028 IRQP2 4 R/W 0x00000000 Contains the interrupt priority setting for Interrupt Source 16 to
Interrupt Source 19.
0x0030 IRQCONN 4 R/W 0x00000000 Used to enable IRQ and FIQ interrupt nesting.
0x0034 IRQCONE 4 R/W 0x00000000 Configures the external interrupt sources as rising edge, falling edge, or
level triggered.
0x0038 IRQCLRE 4 R/W 0x00000000 Used to clear an edge-level-triggered interrupt source.
0x003C
IRQSTAN
4
R/W
0x00000000
This register indicates the priority level of an interrupt that has just
caused an interrupt exception.
0x0100 FIQSTA 4 R 0x00000000 Active FIQ source status.
0x0104 FIQSIG 4 R Current state of all FIQ sources (enabled and disabled).
0x0108 FIQEN 4 R/W 0x00000000 Enabled FIQ sources.
0x010C FIQCLR 4 W 0x00000000 MMR to disable FIQ sources.
0x011C FIQVEC 4 R 0x00000000 This register contains the subroutine address for the currently active FIQ
source.
0x013C FIQSTAN 4 R/W 0x00000000 Indicates the priority level of an FIQ that has just caused an FIQ
exception.
Table 18. System Control Address Base = 0xFFFF0200
Address Name Bytes
Access
Type Default Value Description
0x0220 REMAP
1
1 R/W 0x00 Remap control register. See the Remap Operation section.
0x0230 RSTSTA 1 R/W 0x01 RSTSTA status MMR. See the Reset section.
0x0234 RSTCLR 1 W 0x00 Register for clearing the RSTSTA register.
1
Updated by the kernel.