Datasheet

Table Of Contents
ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 28 of 108
COMPLETE MMR LISTING
In the following MMR tables, addresses are listed in hexadecimal code. Access types include R for read, W for write, and R/W for read
and write.
Table 17. IRQ Address Base = 0xFFFF0000
Address Name Bytes
Access
Type Default Value Description
0x0000 IRQSTA 4 R 0x00000000 Active IRQ source status.
0x0004 IRQSIG 4 R Current state of all IRQ sources (enabled and disabled).
0x0008 IRQEN 4 R/W 0x00000000 Enabled IRQ sources.
0x000C IRQCLR 4 W 0x00000000 MMR to disable IRQ sources.
0x0010 SWICFG 4 W 0x00000000 Software interrupt configuration MMR.
0x0014 IRQBASE 4 R/W 0x00000000 Base address of all vectors. Points to the start of the 64-byte memory block,
which can contain up to 32 pointers to separate subroutine handlers.
0x001C IRQVEC 4 R 0x00000000 This register contains the subroutine address for the currently active
IRQ source.
0x0020 IRQP0 4 R/W 0x00000000 Contains the interrupt priority setting for Interrupt Source 1 to Interrupt
Source 7. An interrupt can have a priority setting of 0 to 7.
0x0024 IRQP1 4 R/W 0x00000000 Contains the interrupt priority setting for Interrupt Source 8 to Interrupt
Source 15.
0x0028 IRQP2 4 R/W 0x00000000 Contains the interrupt priority setting for Interrupt Source 16 to
Interrupt Source 19.
0x0030 IRQCONN 4 R/W 0x00000000 Used to enable IRQ and FIQ interrupt nesting.
0x0034 IRQCONE 4 R/W 0x00000000 Configures the external interrupt sources as rising edge, falling edge, or
level triggered.
0x0038 IRQCLRE 4 R/W 0x00000000 Used to clear an edge-level-triggered interrupt source.
0x003C
IRQSTAN
4
R/W
0x00000000
This register indicates the priority level of an interrupt that has just
caused an interrupt exception.
0x0100 FIQSTA 4 R 0x00000000 Active FIQ source status.
0x0104 FIQSIG 4 R Current state of all FIQ sources (enabled and disabled).
0x0108 FIQEN 4 R/W 0x00000000 Enabled FIQ sources.
0x010C FIQCLR 4 W 0x00000000 MMR to disable FIQ sources.
0x011C FIQVEC 4 R 0x00000000 This register contains the subroutine address for the currently active FIQ
source.
0x013C FIQSTAN 4 R/W 0x00000000 Indicates the priority level of an FIQ that has just caused an FIQ
exception.
Table 18. System Control Address Base = 0xFFFF0200
Address Name Bytes
Access
Type Default Value Description
0x0220 REMAP
1
1 R/W 0x00 Remap control register. See the Remap Operation section.
0x0230 RSTSTA 1 R/W 0x01 RSTSTA status MMR. See the Reset section.
0x0234 RSTCLR 1 W 0x00 Register for clearing the RSTSTA register.
1
Updated by the kernel.