Datasheet

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 27 of 108
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array and is accessed by
indirect addressing through the ARM7 banked registers.
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers, except the core registers, reside
in the MMR area. All shaded locations shown in Figure 12 are
unoccupied or reserved locations and should not be accessed by
user software. Figure 12 shows the full MMR memory map.
The access time for reading from or writing to an MMR
depends on the advanced microcontroller bus architecture
(AMBA) bus used to access the peripheral. The processor has
two AMBA buses: the advanced high performance bus (AHB)
used for system modules and the advanced peripheral bus
(APB) used for a lower performance peripheral. Access to the
AHB is one cycle, and access to the APB is two cycles. All
peripherals on the ADuC706x are on the APB except for the
Flash/EE memory, the GPIOs, and the PWM.
PWM
0xFFFF0FC0
0xFFFFFFFF
0xFFFF0F80
FLASH CONTROL
INTERFACE
0xFFFF0E24
0xFFFF0E00
GPIO
0xFFFF0D50
0xFFFF0D00
SPI
0xFFFF0A14
0xFFFF0A00
I
2
C
0xFFFF0948
0xFFFF0900
UART
0xFFFF0730
0xFFFF0700
DAC
0xFFFF0620
0xFFFF0600
ADC
0xFFFF0570
0xFFFF0500
BAND GAP
REFERENCE
0xFFFF0490
0xFFFF048C
SPI/I
2
C
SELECTION
0xFFFF0470
0xFFFF0450
PLL AND OSCILLATOR
CONTROL
0xFFFF0420
0xFFFF0404
GENERAL-PURPOSE
TIMER
0xFFFF0394
0xFFFF0380
WATCHDOG
TIMER
0xFFFF0370
0xFFFF0360
WAKE-UP
TIMER
0xFFFF0350
0xFFFF0340
GENERAL-PURPOSE
TIMER
0xFFFF0334
0xFFFF0320
REMAP AND
SYSTEM CONTROL
0xFFFF0238
0xFFFF0220
INTERRUPT
CONTROLLER
0xFFFF0140
0xFFFF0000
07079-007
Figure 12. Memory Mapped Registers