Datasheet

Data Sheet ADuC7060/ADuC7061
Rev. D | Page 23 of 108
By default, after a reset, the Flash/EE memory is logically
mapped to Address 0x00000000. It is possible to logically remap
the SRAM to Address 0x00000000 by setting Bit 0 of the remap
MMR located at 0xFFFF0220. To revert Flash/EE to 0x00000000,
Bit 0 of remap is cleared.
It is sometimes desirable to remap RAM to 0x00000000 to optimize
the interrupt latency of the ADuC706x because code can run in
full 32-bit ARM mode and at maximum core speed. Note that,
when an exception occurs, the core defaults to ARM mode.
Remap Operation
When a reset occurs on the ADuC706x, execution starts automati-
cally in the factory programmed internal configuration code.
This so-called kernel is hidden and cannot be accessed by user
code. If the ADuC706x is in normal mode, it executes the power-
on configuration routine of the kernel and then jumps to the
reset vector, Address 0x00000000, to execute the user’s reset
exception routine. Because the Flash/EE is mirrored at the
bottom of the memory array at reset, the reset routine must
always be written in Flash/EE.
The remap command must be executed from the absolute Flash/EE
address and not from the mirrored, remapped segment of memory,
because this may be replaced by SRAM. If a remap operation is
executed while operating code from the mirrored location, pre-
fetch/data aborts can occur, or the user can observe abnormal
program operation. Any kind of reset logically remaps the Flash/EE
memory to the bottom of the memory array.
Remap Register
Name: Remap
Address: 0xFFFF0220
Default value: 0x0000
Access: Read and write
Function: This 8-bit register allows user code to remap
either RAM or Flash/EE space into the bottom
of the ARM memory space starting at
Address 0x00000000.
Table 12. Remap MMR Bit Designations
Bit Description
7:1 Reserved. These bits are reserved and should be written
as 0 by user code.
0 Remap bit.
Set by user to remap the SRAM to 0x00000000.
Cleared automatically after reset to remap the Flash/EE
memory to 0x00000000.
FLASH/EE CONTROL INTERFACE
Serial and JTAG programming use the Flash/EE control
interface, which includes the eight MMRs outlined in this
section. Note that the flash page size is 512 bytes.
FEESTA Register
FEESTA is a read-only register that reflects the status of the
flash control interface as described in Table 13.
Name: FEESTA
Address: 0xFFFF0E00
Default value: 0x0020
Access: Read
Table 13. FEESTA MMR Bit Designations
Bit Description
15:6 Reserved.
5 Reserved.
4 Reserved.
3 Flash interrupt status bit. Set automatically when an
interrupt occurs, that is, when a command is complete
and the Flash/EE interrupt enable bit in the FEEMOD
register is set. Cleared when reading the FEESTA
register.
2
Flash/EE controller busy. Set automatically when the
controller is busy. Cleared automatically when the
controller is not busy.
1 Command fail. Set automatically when a command
completes unsuccessfully. Cleared automatically when
reading the FEESTA register.
0 Command pass. Set by the MicroConverter® when a
command completes successfully. Cleared
automatically when reading the FEESTA register.
FEEMOD Register
FEEMOD sets the operating mode of the flash control interface.
Table 14 lists FEEMOD MMR bit designations.
Name: FEEMOD
Address: 0xFFFF0E04
Default value: 0x0000
Access: Read and write
Table 14. FEEMOD MMR Bit Designations
Bit Description
15:9 Reserved.
8 Reserved. Always set this bit to 1.
7:5 Reserved. Always set these bits to 0 except when
writing keys.
4 Flash/EE interrupt enable.
Set by user to enable the Flash/EE interrupt. The
interrupt occurs when a command is complete.
Cleared by user to disable the Flash/EE interrupt.
3 Erase/write command protection.
Set by user to enable the erase and write commands.
Cleared to protect the Flash/EE against the erase/write
command.
2:0 Reserved. Always set these bits to 0.