Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Revision History
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Terminology
- Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
- Oscillator, PLL, and Power Control
- ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- ADC Status Register
- ADC Interrupt Mask Register
- ADC Mode Register
- Primary ADC Control Register
- Auxiliary ADC Control Register
- ADC Filter Register
- ADC Configuration Register
- Primary Channel ADC Data Register
- Auxiliary Channel ADC Data Register
- Primary Channel ADC Offset Calibration Register
- Auxiliary Channel ADC Offset Calibration Register
- Primary Channel ADC Gain Calibration Register
- Auxiliary Channel Gain Calibration Register
- Primary Channel ADC Result Counter Limit Register
- Primary Channel ADC Result Counter Register
- Primary Channel ADC Threshold Register
- Primary Channel ADC Threshold Counter Limit Register
- Primary Channel ADC Threshold Counter Register
- Primary Channel ADC Accumulator Register
- Excitation Current Sources Control Register
- Example Application Circuits
- DAC Peripherals
- Nonvolatile Flash/EE Memory
- Processor Reference Peripherals
- Timers
- Pulse-Width Modulator
- Pulse-Width Modulator General Overview
- PWMCON Control Register
- PWM0COM0 Compare Register
- PWM0COM1 Compare Register
- PWM0COM2 Compare Register
- PWM0LEN Register
- PWM1COM0 Compare Register
- PWM1COM1 Compare Register
- PWM1COM2 Compare Register
- PWM1LEN Register
- PWM2COM0 Compare Register
- PWM2COM1 Compare Register
- PWM2COM2 Compare Register
- PWM2LEN Register
- PWMCLRI Register
- Pulse-Width Modulator General Overview
- UART Serial Interface
- Baud Rate Generation
- UART Register Definitions
- I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
- I2C Registers
- I2C Master Registers
- I2C Master Control, I2CMCON Register
- I2C Master Status, I2CMSTA, Register
- I2C Master Receive, I2CMRX, Register
- I2C Master Transmit, I2CMTX, Register
- I2C Master Read Count, I2CMCNT0, Register
- I2C Master Current Read Count, I2CMCNT1, Register
- I2C Address 0, I2CADR0, Register
- I2C Address 1, I2CADR1, Register
- I2C Master Clock Control, I2CDIV, Register
- I2C Slave Registers
- I2C Common Registers
- I2C Master Registers
- Serial Peripheral Interface
- General-Purpose I/O
- Hardware Design Considerations
- Outline Dimensions

ADuC7060/ADuC7061 Data Sheet
Rev. D | Page 104 of 108
HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
The ADuC706x operational power supply voltage range is
2.375 V to 2.625 V. Separate analog and digital power supply
pins (AVDD and DVDD, respectively) allow AVDD
to be kept
relatively free of noisy digital signals often present on the
system DVDD line. In this mode, the part can also operate with
split supplies; that is, it can use different voltage levels for each
supply. For example, the system can be designed to operate
with a DVDD voltage level of 2.6 V, whereas the AVDD level
can be at 2.5 V or vice versa. A typical split supply
configuration is shown in Figure 28.
ADuC7060/
ADuC7061
0.1µF
ANALOG
SUPPLY
10µF
AVDD
DVDD
DGND
AGND
0.1µF
+
–
DIGITAL
SUPPLY
10µF
+
–
07079-022
Figure 28. External Dual Supply Connections
As an alternative to providing two separate power supplies, the
user can reduce noise on AVDD by placing a small series
resistor and/or ferrite bead between AVDD and DVDD, and then
decoupling AVDD separately to ground. An example of this
configuration is shown in Figure 29. With this configuration,
other analog circuitry (such as op amps, voltage reference, and
others) can be powered from the AV DD supply line as well.
ADuC7060/
ADuC7061
0.1µF
ANALOG
SUPPLY
10µF
AVDD
DVDD
DGND
AGND
0.1µF
DIGITAL
SUPPLY
BEAD
10µF
+
–
07079-023
Figure 29. External Single Supply Connections
Notice that in both Figure 28 and Figure 29, a large value (10 µF)
reservoir capacitor sits on DVDD, and a separate 10 µF
capacitor sits on AVDD. In addition, local, small value (0.1 µF)
capacitors are located at each AVDD and DVDD pin of the chip.
As per standard design practice, be sure to include all of these
capacitors and ensure that the smaller capacitors are close to the
AVDD pin with trace lengths as short as possible. Connect the
ground terminal of each of these capacitors directly to the
underlying ground plane.
Note that the analog and digital ground pins on the ADuC706x
must be referenced to the same system ground reference point
at all times.
Finally, note that, when the DVDD supply reaches 1.8 V, it must
ramp to 2.25 V in less than 128 ms. This is a requirement of the
internal power-on reset circuitry.