Datasheet

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Table Of Contents

Features
Applications
General Description
Revision History
Functional Block Diagram
Specifications
- Electrical Specifications
- Timing Specifications
  - I2C Timing
  - SPI Timing
Absolute Maximum Ratings
- ESD Caution
Pin Configurations and Function Descriptions
Terminology
Overview of the ARM7TDMI Core
- Thumb Mode (T)
- Multiplier (M)
- EmbeddedICE (I)
  - ARM7 Exceptions
- ARM Registers
- Interrupt Latency
- Memory Organization
- Flash/EE Control Interface
- Memory Mapped Registers
- Complete MMR Listing
- Reset
  - RSTSTA Register
  - RSTCLR Register
Oscillator, PLL, and Power Control
- Clocking System
  - External Crystal Selection
  - External Clock Selection
- Power Control System
  - Power and Clock Control Registers
ADC Circuit Information
- Reference Sources
- Diagnostic Current Sources
- Sinc3 Filter
- ADC Chopping
- Programmable Gain Amplifier
- Excitation Sources
- ADC Low Power Mode
- ADC Comparator and Accumulator
- Temperature Sensor
- ADC MMR Interface
- Example Application Circuits
DAC Peripherals
- DAC
  - Op Amp Mode
- MMR Interface
  - DAC0CON Register
  - DAC0DAT Register
- Using the DAC
Nonvolatile Flash/EE Memory
- Flash/EE Memory Reliability
- Programming
  - Serial Downloading (In-Circuit Programming)
  - JTAG Access
Processor Reference Peripherals
- Interrupt System
- IRQ
- Fast Interrupt Request (FIQ)
- Programmed Interrupts
  - SWICFG
    - SWICFG Register
- Vectored Interrupt Controller (VIC)
- VIC MMRs
Timers
- HR:MIN:SEC: 1/128 Format
- Timer0
- Timer1 or Wake-Up Timer
- Timer2 or Watchdog Timer
- Timer3
Pulse-Width Modulator
- Pulse-Width Modulator General Overview
UART Serial Interface
- Baud Rate Generation
  - Normal 450 UART Baud Rate Generation
  - ADuC706x Fractional Divider
- UART Register Definitions
I2C
- Configuring External Pins for I2C Functionality
- Serial Clock Generation
- I2C Bus Addresses
  - Slave Mode
  - Master Mode
- I2C Registers
Serial Peripheral Interface
- MISO (Master In, Slave Out) Pin
- MOSI (Master Out, Slave In) Pin
- SCLK (Serial Clock I/O) Pin
- Slave Select (P0.0/) Input Pin
- Configuring External Pins for SPI Functionality
- SPI Registers
General-Purpose I/O
- GPxCON Registers
- GPxDAT Registers
- GPxSET Registers
- GPxCLR Registers
- GPxPAR Registers
  - GP0CON1 Control Registers
Hardware Design Considerations
- Power Supplies
Outline Dimensions
- Ordering Guide

ADuC7060/ADuC7061 Data Sheet

Rev. D | Page 100 of 108

Bit Name Description

SPIMEN Master mode enable bit.

Set by user to enable master mode.

Cleared by user to enable slave mode.

SPIEN SPI enable bit.

Set by user to enable the SPI.

Cleared by user to disable the SPI.