Datasheet

ADuC7033
Rev. B | Page 81 of 140
Timer1 Capture Register
Name: T1CAP
Address: 0xFFFF0330
Default Value: 0x00000000
Access: Read only
Function: This 32-bit register holds the 32-bit value captured by an enabled IRQ event.
Timer1 Control Register
Name: T1CON
Address: 0xFFFF0328
Default Value: 0x01000000
Access: Read/write
Function: This 32-bit MMR configures the mode of operation of Timer1.
Table 54. T1CON MMR Bit Designations
Bit Description
31 to 24 8-Bit Postscaler.
By writing to these eight bits, a value is written to the postscaler. Writing 0 is interpreted as a 1.
By reading these eight bits, the current value of the counter is read.
23 Timer1 Enable Postscaler.
Set to enable the Timer1 postscaler. If enabled, interrupts are generated after T1CON[31:24] periods as defined
by T1LD.
Cleared to disable the Timer1 postscaler.
22 to 20 Reserved. These bits are reserved and should be written as 0 by user code.
19
Postscaler Compare Flag. Read only. Set if the number of Timer1 overflows is equal to the number written to the
postscaler.
18 Timer1 Interrupt Source.
Set to select interrupt generation from the postscaler counter.
Cleared to select interrupt generation directly from Timer1.
17 Event Select Bit.
Set by user to enable time capture of an event.
Cleared by user to disable time capture of an event.
16 to 12 Event select range, 0 to 31. The events are described in Table 52.
11 to 9 Clock Select.
000 = core clock (default).
001 = low power 32.768 kHz oscillator.
010 = GPIO_8.
011 = GPIO_5.
8 Count Up.
Set by user for Timer1 to count up.
Cleared by user for Timer1 to count down (default).
7 Timer1 Enable Bit.
Set by user to enable Timer1.
Cleared by user to disable Timer1 (default).
6 Timer1 Mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode (default).