Datasheet

ADuC7033
Rev. B | Page 78 of 140
Timer0 Control Register
Name: T0CON
Address: 0xFFFF030C
Default Value: 0x00000000
Access: Read/write
Function: The 32-bit MMR configures the mode of operation for Timer0.
Table 53. T0CON MMR Bit Designations
Bit Description
31 to 18 Reserved.
17 Event Select Bit.
Set by user to enable time capture of an event.
Cleared by user to disable time capture of an event.
16 to 12 Event Select Range (0 to 31). The events are as described in Table 52.
11 Reserved.
10 to 9 Clock Select.
00 = core clock (default).
01 = low power (32.768 kHz) oscillator.
10 = external (32.768 kHz) watch crystal.
11 = precision (32.768 kHz) oscillator.
8 Count Up. Available in 16-bit mode only.
Set by user for Timer0 to count up.
Cleared by user for Timer0 to count down (default).
7 Timer0 Enable Bit.
Set by user to enable Timer0.
Cleared by user to disable Timer0 (default).
6 Timer0 Mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode (default).
5 Reserved.
4 Timer0 Mode of Operation.
0 = 16-bit operation (default).
1 = 48-bit operation.
3 to 0 Prescaler.
0000 = source clock/1 (default).
0100 = source clock/16.
1000 = source clock/256.
1111 = source clock/32,768.