Datasheet

ADuC7033
Rev. B | Page 74 of 140
TIMERS
The ADuC7033 features five general-purpose timer/counters.
• Timer0, or lifetime timer
• Timer1
• Timer2 or wake-up timer
• Timer3 or watchdog timer
• Timer4 or STI timer
The five timers in their normal mode of operation can be in
either free running mode or periodic mode.
Timers are started by writing data to the control register of the
corresponding timer (TxCON). The counting mode and speed
depend on the configuration chosen in TxCON.
In normal mode, an IRQ is generated each time the value of
the counter reaches 0 when counting down, or each time the
counter value reaches full scale when counting up. An IRQ
can be cleared by writing any value to clear the register of
that particular timer (TxCLRI).
The three timers in their normal mode of operation can be
either free-running or periodic.
In free-running mode, starting with the value in the TxLD
register, the counter decrements/increments from the maximum/
minimum value until zero/full scale and starts again at the
maximum/minimum value. This means that in free-running
mode, TxVAL is not reloaded when the relevant interrupt bit is
set but the count simply rolls over as the counter underflows or
overflows.
In periodic mode, the counter decrements/increments from
the value in the load register (TxLD MMR) until zero/full scale
starts again from this value. This means when the relevant
interrupt bit is set, TxVAL is reloaded with TxLD and counting
starts again from this value.
Loading the TxLD register with zero is not recommended. The
value of a counter can be read at any time by accessing its value
register (TxVAL).
In addition, Timer0, Timer1, and Timer4 each have a capture
register (T0CAP, T1CAP, and T4CAP, respectively) that can
hold the value captured by an enabled IRQ event. The IRQ
events are described in
Table 52.
Table 52. Timer Event Capture
Bit Description
0 Timer0 or lifetime timer
1 Timer1
2 Timer2 or wake-up timer
3 Timer3 or watchdog timer
4 Timer4 or STI timer
5 LIN hardware
6 Flash/EE interrupt
7 PLL lock
8 ADC
9 UART
10 SPI master
11 XIRQ0 (GPIO_0)
12 XIRQ1 (GPIO_5)
13 Reserved
14 IRQ3 (high voltage interrupt)
15 SPI slave
16 XIRQ4 (GPIO_7), see the General-Purpose I/O section
17 XIRQ5 (GPIO_8), see the General-Purpose I/O section
SYNCHRONIZATION OF TIMERS ACROSS
ASYNCHRONOUS CLOCK DOMAINS
Figure 32 shows the interface between user timer MMRs and
the core timer blocks. User code can access all timer MMRs
directly, including TxLD, TxVAL, TxCON, and TxCLRI. Data
must then transfer from these MMRs to the core timers (T0, T1,
T2, T3, and T4) within the timer subsystem. Theses core timers
are buffered from the user MMR interface by the synchroniza-
tion (SYNC) block.
The principal of the SYNC block is to provide a method that
ensures that data and other required control signals can cross
asynchronous clock domains correctly. An example of asyn-
chronous clock domains is the MCU running on the 10 MHz
core clock, and Timer2 running on the low power oscillator
of 32 kHz.