Datasheet

ADuC7033
Rev. B | Page 62 of 140
20
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
018161412108642
(dB)
FREQUENCY (kHz)
06847-025
ADC Calibration
As shown in detail in the top level diagrams (Figure 17 and
Figure 18), the signal flow through all ADC channels can be
described in simple steps.
1. An input voltage is applied through an input buffer (and
PGA in the case of the I-ADC) to the Σ- modulator.
2. The modulator output is applied to a programmable digital
decimation filter.
3. The filter output result is then averaged if chopping is used.
4. An offset value (ADCxOF) is subtracted from the result.
5. This result is scaled by a gain value (ADCxGN).
6. Finally, the result is formatted as twos complement/offset
binary, rounded to 16 bits, or clamped to ±full scale.
Figure 27. Typical Digital Filter Response at f
ADC
= 1 Hz (ADCFLT = 0xBD1F)
Each ADC has a specific offset and gain correction or calibra-
tion coefficient associated with it that are stored in MMR-based
offset and gain registers (ADCxOF and ADCxGN). The offset
and gain registers can be used to remove offsets and gain errors
arising within the part as well as system level offset and gain
errors external to the part.
In general, it is possible to program different values of SF and
AF in the ADCFLT register and achieve the same ADC update
rate. In practical terms, the trade-off with any value of ADCFLT
is frequency response vs. ADC noise. For optimum filter response
and ADC noise when using combinations of SF and AF, best
practice suggests choosing an SF in the range of 16 decimal to
40 decimal, or 0x10 to 0x28, and then increasing the AF value
to achieve the required ADC throughput. Table 43 shows some
common ADCFLT configurations.
These registers are configured at power-on with a factory
programmed calibration value. These factory calibration values
vary from part to part, reflecting the manufacturing variability
of internal ADC circuits. However, these registers can also be
overwritten by user code (only if the ADC is in idle mode) and
are automatically overwritten if an offset or gain calibration
cycle is initiated by the user through the mode bits in the
ADCMDE[2:0] MMR. Two types of automatic calibration are
available to the user, namely, self-calibration and system
calibration.
Table 43. Common ADCFLT Configurations
ADC Mode SF AF Other Config ADCFLT f
ADC
t
SETTLE
Normal 0x1D 0x3F Chop On 0xBF1D 4 Hz 0.5 sec
Normal 0x1F 0x16 Chop On 0x961F 10 Hz 0.2 sec
Normal 0x07 0x00 None 0x0007 1 kHz
3 ms
Normal 0x07 0x00 Sinc3 Modify 0x0087 1 kHz
3 ms
Normal 0x03 0x00 Running Average 0x4003 2 kHz
2 ms
Normal 0x00 0x00 Running Average 0x4000 8 kHz
0.5 ms
Low Power 0x10 0x03 Chop On 0x8310 20 Hz
100 ms
Low Power 0x10 0x09 Chop On 0x8910 10 Hz
200 ms
Low Power 0x1F 0x3D Chop On 0xBD1F 1 Hz 2 sec