Datasheet

ADuC7033
Rev. B | Page 25 of 140
RESET
There are four kinds of reset: external reset, power-on-reset,
watchdog reset, and software reset. The RSTSTA register
indicates the source of the last reset and can also be written by
user code to initiate a software reset event. The bits in this
register can be cleared to 0 by writing to the RSTCLR MMR at
0xFFFF0234. The bit designations in RSTCLR mirror those of
RSTSTA. These registers can be used during a reset exception
service routine to identify the source of the reset. The implica-
tions of all four kinds of reset event are tabulated in Table 12.
RSTSTA Register
Name: RSTSTA
Address: 0xFFFF0230
Default Value: Depends on type of reset
Access: Read/write access
Function: This 8-bit register indicates the source of the
last reset event and can also be written by
user code to initiate a software reset.
RSTCLR Register
Name: RSTCLR
Address: 0xFFFF0234
Access: Write only
Function: This 8-bit write only register clears the
corresponding bit in RSTSTA.
Table 11. RSTSTA/RSTCLR MMR Bit Designations
Bit Description
7 to 4
Not Used. These bits are not used and always
read as 0.
3 External Reset.
Automatically set to 1 when an external reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
2 Software Reset.
Set to 1 by user code to generate a soft-
ware reset.
Cleared by setting the corresponding bit in
RSTCLR.
1
1 Watchdog Timeout.
Automatically set to 1 when a watchdog timeout
occurs.
Cleared by setting the corresponding bit in RSTCLR.
0 Power-On Reset.
Automatically set when a power-on-reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
1
If the software reset bit in RSTSTA is set, any write to RSTCLR that does not
clear this bit generates a software reset.
Table 12. Device Reset Implications
Impact
Reset
Source
Reset
External Pins
to Default
State
Kernel
Executed
Reset All
External MMRs
(Excluding
RSTSTA)
Reset All HV
Indirect
Registers
Peripherals
Reset
Watchdog
Timer Reset
SRAM
Valid
1
RSTSTA
(Status After
Reset Event)
POR Yes Yes Yes Yes Yes Yes Yes/No
2
RSTSTA[0] = 1
Watchdog Yes Yes Yes Yes Yes No Yes RSTSTA[1] = 1
Software Yes Yes Yes Yes Yes No Yes RSTSTA[2] = 1
External Pin Yes Yes Yes Yes Yes No Yes RSTSTA[3] = 1
1
RAM is not valid in the case of a reset following LIN download.
2
The impact on SRAM is dependent on the HVSTA[6] contents if LVF is enabled. When LVF is enabled using HVCFG0[2], SRAM has not been corrupted by the POR reset
mechanism if the LVF Status Bit HVSTA[6] is 1. See the Low Voltage Flag (LVF) section for more information.