Datasheet

ADuC7033
Rev. B | Page 23 of 140
MEMORY ORGANIZATION
The ARM7, a von Neumann architecture, MCU core sees
memory as a linear array of 2
32
byte locations. As shown in
Figure 13, the ADuC7033 maps this into four distinct user areas,
namely: a memory area that can be remapped, an SRAM area, a
Flash/EE area, and a memory mapped register (MMR) area.
• The first 94 kB of this memory space is used as an area into
which the on-chip Flash/EE memory or SRAM can be
remapped.
• The ADuC7033 features a second 4-kB area at the top of
the memory map used to locate the MMRs, through which
all on-chip peripherals are configured and monitored.
• The ADuC7033 features a SRAM size of 6 kB.
• The ADuC7033 features 96 kB of on-chip Flash/EE
memory. 94 kB of on-chip Flash/EE memory are available
to the user. In addition, 2 kB are reserved for the on-chip
kernel.
Any access, either reading or writing, to an area not defined in
the memory map results in a data abort exception.
Memory Format
The ADuC7033 memory organization is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address.
BIT 31
BYTE 2
A
6
2
.
.
.
BYTE 3
B
7
3
.
.
.
BYTE 1
9
5
1
.
.
.
BYTE 0
8
4
0
.
.
.
BIT 0
32 BITS
0xFFFFFFFF
0x00000004
0x00000000
0
6847-009
Figure 12. Little Endian Format
0x00040FFF
0x00040000
0xFFFF0FFF
0xFFFF0000
MMRs
0x00087FFF
0x00080000
FLASH/EE
SRAM
0x00007FFF
0x00000000
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
RESERVED
RESERVED
RESERVED
RESERVED
0
6847-010
Figure 13. ADuC7033 Memory Map
SRAM
The ADuC7033 features 6 kB of SRAM, organized as
1536 locations × 32 bits, that is, 1536 words, which is
located at 0x40000.
The RAM space can be used as data memory and also as
a volatile program space.
ARM code can run directly from SRAM at full clock speed
given that the SRAM array is configured as a 32-bit wide
memory array. SRAM is read/writeable in 8-, 16-, and 32-bit
segments.
Remap
The ARM exception vectors are situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020.
By default, after a reset, the Flash/EE memory is logically
mapped to Address 0x00000000.
It is possible to logically remap the SRAM to Address 0x00000000.
This is accomplished by setting Bit 0 of the SYSMAP0 MMR
located at 0xFFFF0220. To revert Flash/EE memory to
0x00000000, Bit 0 of SYSMAP0 is cleared.
It is sometimes desirable to remap RAM to 0x00000000
to optimize the interrupt latency of the ADuC7033 because
code can run in full 32-bit ARM mode and at maximum core
speed. Note that when an exception occurs, the core defaults to
ARM mode.