Datasheet

ADuC7033
Rev. B | Page 130 of 140
BIT SERIAL DEVICE (BSD) INTERFACE
ADuC7033
UART
LHS
HARDWARE
ADuC7033
RxD
TxD
BPF
INTERNAL
SHORT-CIRCUIT
TRIP REFERENCE
INTERNAL
SHORT-CIRCUIT
SENSE
RESISTOR
OUTPUT
DISABLE
LIN MODE
HVCFG0[1:0]
INPUT
VOLTAGE
THRESHOLD
REFERENCE
LIN ENABLE
(INTERNAL
PULL-UP)
HVCFG0[5]
FOUR LIN
INTERRUPT
SOURCES
BREAK LHSSTA[0]
START LHSSTA[1]
STOP LHSSTA[2]
BREAK
ERROR LHSSTA[4]
VDD
RxD ENABLE
LHSCON0[8]
LHSVAL0
LHSVAL1
LHS INTERRUPT
IRQEN[7]
5MHz
131kHz
LHS
INTERRUPT
LOGIC
VDD
SCR
IO_VSS
OVER
VOLTAGE
PROTECTION
EXTERNAL
LIN PIN
MASTER ECU
PROTECTION
DIODE
MASTER ECU
PULL-UP
C
LOAD
0
6847-048
Figure 52. BSD I/O Hardware Interface
BSD is a pulse-width modulated signal with three possible
states: sync, zero, and one. These are detailed, together with
their associated tolerances, in Table 96. The frame length is
19 bits and communication occurs at 1200 bps ± 3%.
Table 96. BSD Bit Level Description
Parameter Min Typ Max Unit
TxD Rate 1164 1200 1236 bps
Bit Encoding
t
SYNC
1/16 2/16 3/16 t
PERIOD
t
0
5/16 6/16 8/16 t
PERIOD
t
1
10/16 12/16 14/16 t
PERIOD
BSD COMMUNICATION HARDWARE INTERFACE
The ADuC7033 emulates the BSD communication protocol
using a GPIO, an IRQ, and the LIN synchronization hardware,
all of which are under software control.
BSD RELATED MMRS
ADuC7033 emulates the BSD communication protocol using a
software (bit bang) interface with some hardware assistance
form LIN hardware synchronization logic. In effect, the
ADuC7033 BSD interface uses the following protocols:
• An internal GPIO signal (GPIO_12) that is routed to the
external LIN/BSD pin and is controlled directly by
software to generate 0s and 1s.
• When reading bits, the LIN synchronization hardware uses
LHSVAL1 to count the width of the incoming pulses so
that user code can interpret the bits as sync, 0, or 1.
• When writing bits, user code toggles a GPIO pin and uses
the LHSCAP and LHSCMP registers to time pulse widths
and generate an interrupt when the BSD output pulse
width has reached its required width.
The ADuC7033 MMRs required for BSD communication are as
follows:
LHSSTA: LIN hardware sync status register.
LHSCON0: LIN hardware sync control register.
LHSVAL0: LIN hardware sync Timer0 (16-bit timer).
LHSCON1: LIN hardware sync edge setup register.
LHSVAL1: LIN sync break timer.
LHSCAP: LIN sync capture register.
LHSCMP: LIN sync compare register.
IRQEN/CLR: Enable interrupt register.
FIQEN/CLR: Enable fast interrupt register.
GP2DAT: GPIO data register.
GP2SET: GPIO set register.
GP2CLR: GPIO clear register.