Datasheet

ADuC7033
Rev. B | Page 13 of 140
Table 5. SPI Slave Mode Timing (PHASE Mode = 0)
Parameter Description Min Typ Max Unit
t
SS
SS
to SCLK edge
½ t
SL
ns
t
SL
SCLK low pulse width
1
(SPIDIV + 1) × t
HCLK
ns
t
SH
SCLK high pulse width
1
(SPIDIV + 1) × t
HCLK
ns
t
DAV
Data output valid after SCLK edge
2
(3 × t
UCLK
) + (2 × t
HCLK
) ns
t
DSU
Data input setup time before SCLK edge 0 ns
t
DHD
Data input hold time after SCLK edge
2
4 × t
UCLK
ns
t
DF
Data output fall time 3.5 ns
t
DR
Data output rise time 3.5 ns
t
SR
SCLK rise time 3.5 ns
t
SF
SCLK fall time 3.5 ns
t
DOCS
Data output valid after SS
edge
2
(3 × t
UCLK
) + (2 × t
HCLK
) ns
t
SFS
SS
high after SCLK edge
½ t
SL
ns
1
t
HCLK
depends on the clock divider (CD) bits in POWCON MMR. t
HCLK
= t
UCLK
/2
CD
.
2
t
UCLK
= 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
SCLK
(POLARITY = 0)
SS
SCLK
(POLARITY = 1)
t
SH
t
CS
t
SL
t
SR
t
SF
t
SFS
MOSI
MSB IN BITS [6:1] LSB IN
t
DSU
t
DHD
t
DAV
MISO
LSBBITS [6:1]MSB
t
DF
t
DR
t
DOCS
06847-005
Figure 5. SPI Slave Mode Timing (PHASE Mode = 0)