Datasheet

ADuC7033

Rev. B | Page 124 of 140

Bit Description

7 Sync Timer Stop Edge Type Bit.

Cleared to 0 by user code to stop the sync timer on the falling edge count configured through the LHSCON1[7:4]

Set to 1 by user code to stop the sync timer on the rising edge count configured through the LHSCON1[7:4] register.

6 Mode of Operation Bit.

Cleared to 0 by user code to select LIN mode of operation.

Set to 1 by user code to select BSD mode of operation.

5 Enable Compare Interrupt Bit.

Cleared to 0 by user code to disable compare interrupts.

Set to 1 by user code to generate an LHS interrupt (IRQEN[7]) when the value in LHSVAL0 (LIN synchronization bit timer)

= the value in the LHSCMP register. The LHS Compare Interrupt Bit LHSSTA[3] is set when this interrupt occurs. This

configuration is used in BSD write mode to allow user code to correctly time the output pulse widths of BSD bits to be

transmitted.

4 Enable Stop Interrupt.

Cleared to 0 by user code to disable interrupts when a stop condition occurs.

Set to 1 by user code to generate an interrupt when a stop condition occurs.

3 Enable Start Interrupt.

Cleared to 0 by user code to disable interrupts when a start condition occurs.

Set to 1 by user code to generate an interrupt when a start condition occurs.

2 LIN Sync Enable Bit.

Cleared to 0 by user code to disable LHS functionality.

Set to 1 by user code to enable LHS functionality.

1 Edge Counter Clear Bit.

Set to 1 by user code to clear the internal edge counters in the LHS peripheral.

This bit is automatically cleared to 0 after a 15 s delay.

0 LHS Reset Bit.

Set to 1 by user code to reset all LHS logic to default conditions.

This bit is automatically cleared to 0 after a 15 s delay.