Datasheet

ADuC7033
Rev. B | Page 108 of 140
UART SERIAL INTERFACE
The ADuC7033 features a 16,450-compatible UART. The UART
is a full-duplex, universal, asynchronous receiver/transmitter. A
UART performs serial-to-parallel conversion on data characters
received from a peripheral device, and parallel-to-serial conver-
sion on data characters received from the ARM7TDMI. The
UART features a fractional divider that facilitates high accuracy
baud rate generation and a network addressable mode. The
UART functionality is available on the GPIO_5/RxD and
GPIO_6/TxD pins of the ADuC7033.
The serial communication adopts an asynchronous protocol
that supports various word length, stop bits, and parity genera-
tion options selectable in the configuration register.
BAUD RATE GENERATION
The ADuC7033 features two methods of generating the UART
baud rate: normal 450 UART baud rate generation and ADuC7033
fractional divider. These methods are detailed in the Normal
450 UART Baud Rate Generation section and the Fractional
Divider section.
Normal 450 UART Baud Rate Generation
The baud rate is a divided version of the core clock using the
value in the COMDIV0 and COMDIV1 MMRs (16-bit value,
DL). The standard baud rate generator formula is
DL
rateBaud
×××
=
2162
MHz48.20
CD
(1)
Table 79 lists common baud rate values.
Table 79. Baud Rate Using the Standard Baud Rate Generator
Baud Rate CD DL Actual Baud Rate % Error
9600 0 0x43 9552 0.50
19,200 0 0x21 19,394 1.01
115,200 0 0x6 106,667 7.41
9600 3 0x8 10,000 4.17
19,200 3 0x4 20,000 4.17
115,200 3 0x1 80,000 30.56
Fractional Divider
The fractional divider combined with the normal baud rate gen-
erator allows the generation of accurate, high speed baud rates.
/2
/(M+N/2048)
/16DL
UART
CORE
CLOCK
FBEN
06847-038
Figure 42. Fractional Divider Baud Rate Generation
Calculation of the baud rate using a fractional divider is as
follows:
)
2048
(2162
MHz48.20
CD
N
MDL
rateBaud
+××××
=
(2)
2162
MHz48.20
2048
CD
××××
=+
DLrateBaud
N
M
Table 80 lists common baud rate values.
Table 80. Baud Rate Using the Fractional Baud Rate Generator
Baud
Rate CD DL M N
Actual
Baud Rate % Error
9600 0 0x42 1 21 9598.55 0.015
19,200 0 0x21 1 21 19,197.09 0.015
115,200 0 0x5 1 228 115,177.51 0.0195
UART REGISTER DEFINITION
The UART interface consists of the following nine registers:
• COMTX: 8-bit transmit register
• COMRX: 8-bit receive register
• COMDIV0: divisor latch (low byte)
• COMDIV1: divisor latch (high byte)
• COMCON0: line control register
• COMSTA0: line status register
• COMIEN0: interrupt enable register
• COMIID0: interrupt identification register
• COMDIV2: 16-bit fractional baud divide register
COMTX, COMRX, and COMDIV0 share the same address
location. COMTX and COMRX can be accessed when Bit 7 in
the COMCON0 register is cleared. COMDIV0 can be accessed
when Bit 7 of COMCON0 is set.