Integrated, Precision Battery Sensor for Automotive ADuC7033 FEATURES Memory 96 kB Flash/EE memory, 6 kB SRAM 10,000-cycle Flash/EE endurance, 20-year Flash/EE retention In-circuit download via JTAG and LIN On-chip peripherals LIN 2.
ADuC7033 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Synchronization of Timers Across Asynchronous Clock Domains ...................................................................................... 74 Functional Block Diagram .............................................................. 1 Programming the Timers ..........
ADuC7033 REVISION HISTORY 10/10—Rev. A to Rev. B Changes to Table 32 ........................................................................47 Changes to Timers Section ............................................................74 Added Synchronization of Timers across Asynchronous Clock Domains Section, Figure 32, and Figure 33 .................................74 Added Programming the Timers Section ....................................75 11/09—Rev. 0 to Rev. A Removed LFCSP ..............................
ADuC7033 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3.5 V to 18 V, VREF = 1.2 V internal reference, fCORE = 10.24 MHz driven from external 32.768 kHz watch crystal or on-chip precision oscillator, all specifications TA = −40°C to +115°C, unless otherwise noted. Table 1.
ADuC7033 Parameter Total Gain Error1, 3, 7, 13, 14 Gain Drift Output Noise1, 10, 15 Temperature Channel No Missing Codes1 Integral Nonlinearity1 Offset Error3, 5, 16, 17 Offset Error1, 3 Offset Error Drift Total Gain Error1, 3, 13 Gain Drift Output Noise1 ADC SPECIFICATIONS ANALOG INPUT Current Channel Absolute Input Voltage Range Input Voltage Range18, 19 Input Leakage Current1 Input Offset Current1, 21 Voltage Channel Absolute Input Voltage Range Input Voltage Range VBAT Input Current Temperature Channe
ADuC7033 Parameter ADC Low Power Reference Internal VREF Initial Accuracy Initial Accuracy1 Temperature Coefficient1, 22 RESISTIVE ATTENUATOR Divider Ratio Resistor Mismatch Drift ADC GROUND SWITCH Resistance Input Current TEMPERATURE SENSOR25 Accuracy POWER-ON RESET (POR) POR Trip Level POR Hysteresis RESET Timeout from POR LOW VOLTAGE FLAG (LVF) LVF Level POWER SUPPLY MONITOR (PSM) PSM Trip Level WATCHDOG TIMER (WDT) Timeout Period1 Timeout Step Size FLASH/EE MEMORY1 Endurance26 Data Retention27 DIGITAL
ADuC7033 Parameter MCU START-UP TIME At Power-On After Reset Event From MCU Power-Down Oscillator Running Wake Up from Interrupt Wake Up from LIN Crystal Powered Down Wake Up from Interrupt Internal PLL Lock Time LIN INPUT/OUTPUT GENERAL Baud Rate VDD Input Capacitance Input Leakage Current LIN Comparator Response Time1 ILIN DOM MAX ILIN_PAS_REC ILIN1 ILIN_PAS_DOM1 ILIN_NO_GND29 VLIN_DOM1 VLIN_REC1 VLIN_CNT1 VHYS1 VLIN_DOM_DRV_LOSUP1 RL 500 Ω RL 1000 Ω VLIN_DOM_DRV_HISUP1 RL 500 Ω RL 1000 Ω VLIN_RECESSIVE V
ADuC7033 Parameter D2 BSD INPUT/OUTPUT30 Baud Rate Input Leakage Current VOL, Output Low Voltage VOH, Output High Voltage Io(sc), Short-Circuit Output Current VINL, Input Low Voltage VINH, Input High Voltage WAKE VDD1 Input Leakage Current VOH31 VOL31 VIH VIL Monoflop Timeout Io(sc), Short-Circuit Output Current SERIAL TEST INTERFACE Baud Rate Input Leakage Current VDD VOH VOL VIH VIL PACKAGE THERMAL SPECIFICATIONS Thermal Shutdown1, 32 θJA, Thermal Impedance33 POWER REQUIREMENTS Power Supply Voltages VDD
ADuC7033 1 Not guaranteed by production test, but by design and/or characterization data at production release. Valid for current ADC gain setting of PGA = 4 to 64. 3 These numbers include temperature drift. 4 Tested at gain range = 4; self-offset calibration removes this error at the operating temperature. 5 Measured with an internal short after an initial offset calibration. 6 Measured with an internal short. 7 These numbers include internal reference temperature drift. 8 Factory calibrated at gain = 1.
ADuC7033 TIMING SPECIFICATIONS SPI Timing Specifications Table 2. SPI Master Mode Timing (PHASE Mode = 1) Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF 2 Min Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK Max (2 × tUCLK) + (2 × tHCLK) 0 3 × tUCLK 3.5 3.5 3.5 3.5 tHCLK depends on the clock divider (CD) bits in POWCON MMR. tHCLK = tUCLK/2CD. tUCLK = 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
ADuC7033 Table 3. SPI Master Mode Timing (PHASE Mode = 0) Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF 2 Min Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK Max (2 × tUCLK) + (2 × tHCLK) ½ tSL 0 3 × tUCLK 3.5 3.5 3.5 3.5 tHCLK depends on the clock divider (CD) bits in POWCON MMR. tHCLK = tUCLK/2CD. tUCLK = 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
ADuC7033 Table 4. SPI Slave Mode Timing (PHASE Mode = 1) Parameter t SS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS 2 Min SCLK low pulse width1 SCLK high pulse width1 Data output valid after SCLK edge2 Data input setup time before SCLK edge Data input hold time after SCLK edge2 Data output fall time Data output rise time SCLK rise time SCLK fall time SS high after SCLK edge Typ ½ tSL Max Unit ns (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK (3 × tUCLK) + (2 × tHCLK) 0 4 × tUCLK 3.5 3.5 3.5 3.
ADuC7033 Table 5.
ADuC7033 LIN Timing Specifications RECESSIVE tBIT tBIT tBIT TRANSMIT INPUT TO TRANSMITTING NODE DOMINANT tLIN_DOM (MAX) tLIN_REC (MIN) THRESHOLDS OF RECEIVING NODE 1 THREC (MAX) THDOM (MAX) VSUP LIN BUS (TRANSCEIVER SUPPLY OF TRANSMITTING NODE) THRESHOLDS OF RECEIVING NODE 2 THREC (MIN) THDOM (MIN) tLIN_DOM (MIN) tLIN_REC (MAX) RxD (OUTPUT OF RECEIVING NODE 1) tRX_PDF tRX_PDR tRX_PDR Figure 6. LIN 2.0 Timing Specification Rev.
ADuC7033 ABSOLUTE MAXIMUM RATINGS TA = −40°C to +115°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6.
ADuC7033 IO_VSS STI NC VSS NC VDD WU NC NC NC XTAL2 47 46 45 44 43 42 41 40 39 38 37 34 DGND GPIO_7/IRQ4 4 33 REG_DVDD GPIO_8/IRQ5 5 32 NC 31 GPIO_4/ECLK 30 GPIO_3/MOSI DGND 8 29 GPIO_2/MISO NC 9 28 GPIO_1/SCLK TDO 10 27 GPIO_0/IRQ0/SS NTRST 11 26 NC TMS 12 25 NC IIN– 20 IIN+ 19 VTEMP 18 NC 17 NC 16 TOP VIEW (Not to Scale) GND_SW 15 TDI 7 VREF 14 ADuC7033 VBAT 13 TCK 6 NC = NO CONNECT REG_AVDD 24 DGND GPIO_6/TxD 3 NC 23 XTAL1 35 AGND 22 36
ADuC7033 Pin No. 7 Mnemonic TDI Type 1 I 8, 34, 35 9, 16, 17, 23, 25, 26, 32, 38 to 40, 43, 45 10 DGND NC S TDO O 11 NTRST I 12 TMS I 13 14 VBAT VREF I I 15 GND_SW I 18 19 20 21, 22 24 27 VTEMP IIN+ IIN− AGND REG_AVDD GPIO_0/IRQ0/SS I I I S S I/O 28 GPIO_1/SCLK I/O 29 GPIO_2/MIS0 I/O 30 GPIO_3/MOSI I/O Description JTAG Test Data Input. This data input pin is one of the standard 5-pin JTAG debug ports on the part.
ADuC7033 Pin No. 31 Mnemonic GPIO_4/ECLK Type 1 I/O 33 36 37 REG_DVDD XTAL1 XTAL2 S O I 41 WU I/O 42 44 46 VDD VSS STI S S I/O 47 48 IO_VSS LIN/BSD S I/O 1 Description General-Purpose Digital Input/Output 4, Clock. This is a multifunction pin. By default and after power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor. This pin remains unconnected when not in use.
ADuC7033 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 –0.5 –0.5 CORE OFF VDD = 4V –1.0 OFFSET (µV) OFFSET (µV) –1.0 –1.5 –2.0 VDD = 18V –1.5 CD = 1 –2.0 –2.5 –2.5 –3.0 –3.0 0 50 100 TEMPERATURE (°C) Figure 8. ADC Current Channel Offset vs. Temperature, 10 MHz MCU 0 –0.5 –1.0 –1.5 +25°C –2.0 +115°C –2.5 –3.0 –3.5 0 5 10 15 20 VDD (V) 06847-057 OFFSET (µV) –40°C Figure 9. ADC Current Channel Offset vs. VDD (10 MHz, MCU) Rev. B | Page 19 of 140 –3.
ADuC7033 TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC, after the ADC settles. The sigma-delta (Σ-Δ) conversion techniques used on this part mean that while the ADC front-end signal is oversampled at a relatively high sample rate, a subsequent digital filter is used to decimate the output giving a valid 16-bit data conversion result at output rates from 1 Hz to 8 kHz.
ADuC7033 THEORY OF OPERATION The ADuC7033 is a complete system solution for battery monitoring in 12 V automotive applications. The device integrates all of the required features to precisely and intelligently monitor, process, and diagnose 12 V battery parameters, including battery current, voltage, and temperature, over a wide range of operating conditions. Minimizing external system components, the device is powered directly from the 12 V battery.
ADuC7033 • • • • Normal interrupt (IRQ). This is provided to service general-purpose interrupt handling of internal and external events. Fast interrupt (FIQ). This is provided to service data transfer or a communication channel with low latency. FIQ has priority over IRQ. Memory abort (prefetch and data). Attempted execution of an undefined instruction. Software interrupt (SWI) instruction that can be used to make a call to an operating system. in Figure 11.
ADuC7033 MEMORY ORGANIZATION SRAM The ARM7, a von Neumann architecture, MCU core sees memory as a linear array of 232 byte locations. As shown in Figure 13, the ADuC7033 maps this into four distinct user areas, namely: a memory area that can be remapped, an SRAM area, a Flash/EE area, and a memory mapped register (MMR) area. The ADuC7033 features 6 kB of SRAM, organized as 1536 locations × 32 bits, that is, 1536 words, which is located at 0x40000.
ADuC7033 Remap Operation SYSMAP0 Register When a reset occurs on the ADuC7033, execution starts automatically in the factory programmed internal configuration code. This so-called kernel is hidden and cannot be accessed by user code. If the ADuC7033 is in normal mode, it executes the power-on configuration routine of the kernel and then jumps to the reset vector, Address 0x00000000, to execute the user’s reset exception routine.
ADuC7033 RESET RSTCLR Register There are four kinds of reset: external reset, power-on-reset, watchdog reset, and software reset. The RSTSTA register indicates the source of the last reset and can also be written by user code to initiate a software reset event. The bits in this register can be cleared to 0 by writing to the RSTCLR MMR at 0xFFFF0234. The bit designations in RSTCLR mirror those of RSTSTA.
ADuC7033 FLASH/EE MEMORY The ADuC7033 incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable memory space. Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased, the erase being performed in page blocks. Thus, Flash memory is often and more correctly referred to as Flash/EE memory.
ADuC7033 User software must ensure that the Flash/EE memory controller has completed any erase or write cycle before the PLL is powered down. If the PLL is powered down before an erase or write cycle is completed, the Flash/EE page or byte may be corrupted. The following sections provide detailed descriptions of the bit designations for each of the Flash/EE memory control MMRs.
ADuC7033 Command Sequence for Executing a Mass Erase Giving the significance of the mass erase command, a specific code sequence must be executed to initiate this operation. 1. 2. 3. 4. Set Bit 3 in FEExMOD. Write 0xFFC3 in FEExADR Write 0x3CFF in FEExDAT Run the Mass Erase Command 0x06 in FEExCON To run the mass erase command via FEE0CON, write protection on the lower 64 kB must be disabled, that is, FEE1HID/FEE1PRO are set to 0xFFFFFFFF.
ADuC7033 FEE0ADR and FEE1ADR Registers FEE0DAT and FEE1DAT Registers Name: FEE0ADR and FEE1ADR Name: FEE0DAT and FEE1DAT Address: 0xFFFF0E10 and 0xFFFF0E90 Address: 0xFFFF0E0C and 0xFFFF0E8C Default Value: 0x0000 (FEE1ADR). For FEE0ADR, see the System Identification FEE0ADR section. Default Value: 0x0000 Access: Read/write Access: Read/write Function: This 16-bit register dictates the address upon which any Flash/EE command executed via FEExCON acts.
ADuC7033 FLASH/EE MEMORY SECURITY The 94 kB of Flash/EE memory available to the user can be read and write protected using the FFE0HID and FEE1HID registers. In Block0, the FEE0HID MMR protects the 30 kB of Flash/EE memory. Bit 0 to Bit 28 of this register protect Page 0 to Page 57 from writing. Each bit protects two pages, that is, 1 kB. Bit 29 to Bit 30 protect Page 58 and Page 59 respectively, that is, each bit write protects a single page of 512 bytes.
ADuC7033 Block1, Flash/EE Memory Protection Registers Name: FEE1HID and FEE1PRO Address: 0xFFFF0EA0 (for FEE1HID) and 0xFFFF0E9C (for FEE1PRO) Default Value: 0xFFFFFFFF (for FEE1HID) and 0x00000000 (for FEE1PRO) Access: Read/write access Function: These registers are written by user code to configure the protection of the Flash/EE memory. Table 17. FEE1HID and FEE1PRO MMR Bit Designations Bit 31 30 29 to 0 Description Read Protection.
ADuC7033 In summary, there are three levels of protection. Permanent Protection Temporary Protection Set and remove temporary protection by writing directly into the FEExHID MMR. This register is volatile and therefore protection is only in place while the part remains powered on. This protection is not reloaded after a power cycle. Set permanent protection via FEExPRO, similarly to keyed permanent protection, the only difference is that the Software Key 0xDEADDEAD is used.
ADuC7033 FLASH/EE MEMORY RELIABILITY Execution from SRAM The Flash/EE memory array on the part is fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. Fetching instructions from SRAM takes one clock cycle because the access time of the SRAM is 2 ns, and a clock cycle is 49 ns minimum. However, if the instruction involves reading or writing data to memory, one extra cycle must be added if the data is in SRAM.
ADuC7033 ADuC7033 KERNEL The ADuC7033 also features an on-chip LIN downloader. The ADuC7033 features an on-chip kernel resident in the top 2 kB of the Flash/EE code space. After any reset event, this kernel copies the factory calibrated data from the manufacturing data space into the various on-chip peripherals. The peripherals calibrated by the kernel are as follows: A flowchart of the execution of the kernel is shown in Figure 15.
ADuC7033 INITIALIZE ON-CHIP PERIPHERALS TO FACTORY CALIBRATED STATE NO NO PAGE ERASED? 0x14 = 0xFFFFFFFF JTAG MODE? NTRST = 1 KEY PRESENT? 0x14 = 0x27011970 YES YES NO YES CHECKSUM PRESENT? 0x14 = CHECKSUM YES EXECUTE USER CODE NO FLAG PAGE 0 ERROR NO NO YES RESET COMMAND 06847-013 LIN COMMAND Figure 15. ADuC7033 Kernel Flowchart Rev.
ADuC7033 MEMORY MAPPED REGISTERS 0xFFFFFFFF The memory mapped register (MMR) space is mapped into the top 4 kB of the MCU memory space and accessed by indirect addressing, load, and store commands through the ARM7 banked registers. An outline of the memory mapped register bank for the ADuC7033 is shown in Figure 16. 0xFFFF0E00 0xFFFF1000 FLASH CONTROL INTERFACE 0xFFFF0D50 GPIO 0xFFFF0D00 0xFFFF0A14 SPI 0xFFFF0A00 The MMR space provides an interface between the CPU and all on-chip peripherals.
ADuC7033 COMPLETE MMR LISTING In the following MMR tables, addresses are listed in hex code. Access types include R for read, W for write, and RW for read and write. Table 19. IRQ Address Base = 0xFFFF0000 Address 0x0000 0x0004 Name IRQSTA IRQSIG1 Byte 4 4 Access Type R R 0x0008 0x000C 0x0010 IRQEN IRQCLR SWICFG 4 4 4 RW W W 0x00000000 0x0100 0x0104 FIQSTA FIQSIG1 4 4 R R 0x00000000 0x0108 0x010C FIQEN FIQCLR 4 4 RW W 0x00000000 1 Default Value 0x00000000 Description Active IRQ Source.
ADuC7033 Address 0x0340 Name T2LD Byte 4 Access Type RW Default Value 0x00000000 0x0344 T2VAL 4 R 0xFFFFFFFF 0x0348 T2CON 2 RW 0x0000 0x034C T2CLRI 1 W N/A 0x0360 T3LD 2 RW 0x0040 0x0364 T3VAL 2 R 0x0040 0x0368 T3CON 2 RW 0x0000 0x036C T3CLRI1 1 W N/A 0x0380 T4LD 2 RW 0x0000 0x0384 T4VAL 2 R 0xFFFF 0x0388 T4CON 4 RW 0x00000000 0x038C T4CLRI 1 W N/A 0x0390 T4CAP 2 R 0x0000 1 Description Timer2 Load Register.
ADuC7033 Table 23.
ADuC7033 Table 24. UART Base Address = 0xFFFF0700 Address 0x0700 0x0700 0x0700 Name COMTX COMRX COMDIV0 Byte 1 1 1 Access Type W R RW Default Value N/A 0x00 0x00 0x0704 COMIEN0 1 RW 0x00 0x0704 COMDIV1 1 RW 0x00 0x0708 COMIID0 1 R 0x01 0x070C 0x0710 0x0714 0x072C COMCON0 COMCON1 COMSTA0 COMDIV2 1 1 1 2 RW RW R RW 0x00 0x00 0x60 0x0000 Description UART Transmit Register. See the UART TX Register section. UART Receive Register. See the UART RX Register section.
ADuC7033 Table 27. STI Base Address = 0xFFFF0880 Address 0x0880 0x0884 Name STIKEY0 STICON Byte 4 2 Access Type W RW Default Value N/A 0x0000 0x0888 STIKEY1 4 W N/A 0x088C 0x0890 0x0894 STIDAT0 STIDAT1 STIDAT2 2 2 2 RW RW RW 0x0000 0x0000 0x0000 Description STICON Prewrite Key. See the Serial Test Interface Key0 Register section. Serial Test Interface Control MMR. See the Serial Test Interface Control Register section. STICON Postwrite Key.
ADuC7033 Table 30.
ADuC7033 16-BIT, Σ-Δ ANALOG-TO-DIGITAL CONVERTERS The ADuC7033 incorporates two independent sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), namely: the current channel ADC (I-ADC) and the voltage/temperature channel ADC (V/T-ADC). These precision measurement channels integrate on-chip buffering, a programmable gain amplifier, 16-bit, Σ-Δ modulators, and digital filtering for precise measurement of current, voltage, and temperature variables in 12 V automotive battery systems.
Figure 17. Current ADC, Top Level Overview Rev. B | Page 44 of 140 06847-015 VREF/136 VOLTAGE INPUT. ANALOG INPUT DIAGNOSTIC VOLTAGE SOURCE GND VREF/136 IIN– IIN+ REG_AVDD REG_AVDD TWO 50µA IIN+ AND IIN– CURRENT SOURCES. ANALOG INPUT DIAGNOSTIC CURRENT SOURCES CHOP BUF THE INTERNAL 5ppm/°C REFERENCE IS ROUTED TO THE ADC BY DEFAULT. AN EXTERNAL REFERENCE ON THE VREF PIN CAN ALSO BE SELECTED.
ADuC7033 The external battery voltage (VBAT) is routed to the ADC input via an on-chip, high voltage (divide-by-24), resistive attenuator. This must be enabled/disabled through HVCFG1[7]. VOLTAGE/TEMPERATURE CHANNEL ADC (V/T-ADC) The voltage/temperature channel ADC (V/T-ADC) converts additional battery parameters such as voltage and temperature.
ADuC7033 The ADuC7033 features an integrated ground switch pin, GND_SW, Pin15. This switch allows the user to dynamically disconnect ground from external devices. It allows either a direct connection to ground, or a connection to ground using a 20 kΩ resistor. This additional resistor can be used to reduce the number of external components required for an NTC circuit. The ground switch feature can be used for reducing power consumption on application specific boards.
ADuC7033 ADC NOISE PERFORMANCE TABLES Table 32, Table 33, and Table 34 list the output rms noise in μV for some typical output update rates on the I- and V/T-ADCs. The numbers are typical and are generated at a differential input voltage of 0 V. The output rms noise is specified as the standard deviation (or 1 sigma) of the distribution of ADC output codes collected when the ADC input voltage is at a dc voltage. It is expressed as μV rms. Table 32.
ADuC7033 ADC MMR INTERFACE The ADC is controlled and configured through a number of MMRs described in detail in the following sections. All bits defined in the top eight MSBs (Bits[15:8]) of the MMR are used as flags only and do not generate interrupts. All bits defined in the lower eight LSBs (Bits[7:0]) of this MMR are logic OR’ed to produce a single ADC interrupt to the MCU core. In response to an ADC interrupt, user code should interrogate the ADCSTA MMR to determine the source of the interrupt.
ADuC7033 Bit 2 1 0 Description Temperature Conversion Result Ready Bit. If the temperature channel ADC is enabled, this bit is set by hardware as soon as a valid temperature conversion result is written in the temperature data register (ADC2DAT MMR). It is also set at the end of a calibration. Cleared by reading either ADC2DAT or ADC0DAT. Voltage Conversion Result Ready Bit.
ADuC7033 ADC Mode Register Name: ADCMDE Address: 0xFFFF0508 Default Value: 0x00 Access: Read/write Function: The ADC Mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem. Table 36. ADCMDE MMR Bit Designations Bit 7 6 5 4 to 3 2 to 0 Description Not Used. This bit is reserved for future functionality and should be written as 0 by user code. 20 kΩ Resistor Select. Set to 1 to select the 20 kΩ resistor as shown in Figure 20.
ADuC7033 Current Channel ADC Control Register Name: ADC0CON Address: 0xFFFF050C Default Value: 0x0000 Access: Read/write Function: The current channel ADC control MMR is a 16-bit register that is used to configure the I-ADC. Note: If the current ADC is reconfigured via ADC0CON, the voltage ADC and temperature ADC are also reset. Table 37. ADC0CON MMR Bit Designations Bit 15 14, 13 12 to 10 9 8 7, 6 5, 4 3 to 0 Description Current Channel ADC Enable.
ADuC7033 Voltage/Temperature Channel ADC Control Register Name: ADC1CON Address: 0xFFFF0510 Default Value: 0x0000 Access: Read/write Function: The voltage/temperature channel ADC control MMR is a 16-bit register that is used to configure the V/T-ADC. Note: When enabling/disabling the voltage/temperature ADC, the voltage attenuator must also be enabled/disabled via HVCFG1[7]. Table 38.
ADuC7033 ADC Filter Register Name: ADCFLT Address: 0xFFFF0518 Default Value: 0x0007 Access: Read/write Function: The ADC Filter MMR is a 16-bit register that controls the speed and resolution of the on-chip ADCs. Note: If ADCFLT is modified, the current and voltage/temperature ADCs are reset. Table 39. ADCFLT MMR Bit Designations Bit 15 14 13 to 8 7 6 to 0 Description Chop Enable. Set by the user to enable system chopping of all active ADCs.
ADuC7033 Table 40. ADC Conversion Rates and Settling Times Chop Enabled No Averaging Factor No Running Average No No No No tSETTLING 1 fADC 512,000 [SF + 1] × 64 3 f ADC Yes 512,000 [SF + 1] × 64 4 f ADC Yes No 512,000 [SF + 1] × 64 × [3 + AF ] 1 f ADC No Yes Yes 512,000 [SF + 1] × 64 × [3 + AF ] 2 f ADC Yes N/A N/A 512,000 [SF + 1]× 64 ×[3 + AF ] + 3 2 f ADC 1 An additional time of approximately 60 μs per ADC is required before the first ADC is available. Table 41.
ADuC7033 ADC Configuration Register Name: ADCCFG Address: 0xFFFF051C Default Value: 0x00 Access: Read/write Function: The 8-bit ADC Configuration MMR controls extended functionality related to the on-chip ADCs. Table 42. ADCCFG MMR Bit Designations Bit 7 6, 5 4, 3 2 1 0 Description Analog Ground Switch Enable. Set to 1 by user software to connect the external GND_SW pin (Pin 15) to an internal analog ground reference point.
ADuC7033 Current Channel ADC Data Register Current Channel ADC Offset Calibration Register Name: ADC0DAT Name: ADC0OF Address: 0xFFFF0520 Address: 0xFFFF0530 Default Value: 0x0000 Default Value: Part specific, factory programmed Access: Read only Access: Read/write access Function: This ADC Data MMR holds the 16-bit conversion result from the I-ADC. The ADC does not update this MMR if the ADC0 conversion result ready bit (ADCSTA[0]) is set.
ADuC7033 Temperature Channel ADC Offset Calibration Register Voltage Channel Gain Calibration Register Name: ADC2OF Name: ADC1GN Address: 0xFFFF0538 Address: 0xFFFF0540 Default Value: Part specific, factory programmed Default Value: Part specific, factory programmed Access: Read/write Access: Read/write Function: This ADC Offset MMR holds a 16-bit offset calibration coefficient for the temperature channel. The register is configured at power-on with a factory default value.
ADuC7033 Current Channel ADC Result Counter Limit Register Current Channel ADC Threshold Count Limit Register Name: ADC0RCL Name: ADC0TCL Address: 0xFFFF0548 Address: 0xFFFF0554 Default Value: 0x0001 Default Value: 0x01 Access: Read/write Access: Read/write Function: This 16-bit MMR sets the number of conversions required before an ADC interrupt is generated. By default this register is set to 0x01.
ADuC7033 Low Power Voltage Reference Scaling Factor enables the ADCs to provide regular conversion results at a rate of between 4 Hz and 8 kHz (see the ADC Filter Register section). Both channels are under full control of the MCU and can be reconfigured at any time. The default ADC update rate for all channels in this mode is 1.0 kHz. Name: ADCREF Address: 0xFFFF057C Default Value: Part specific, factory programmed Access: Read/write.
ADuC7033 0 ADC Comparator and Accumulator ADC Sinc3 Digital Filter Response The overall frequency response on all ADuC7033 ADCs is dominated by the low-pass filter response of the on-chip Sinc3 digital filters. The Sinc3 filters are used to decimate the ADC Σ-Δ modulator output data bit stream to generate a valid 16-bit data result. The digital filter response is identical for all ADCs and is configured via the 16-bit ADC filter (ADCFLT) register.
0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 0 2 4 6 8 10 12 14 16 18 20 22 24 FREQUENCY (kHz) –100 06847-021 –100 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (Hz) 06847-023 (dB) (dB) ADuC7033 Figure 23. Typical Digital Filter Response at fADC = 8 kHz (ADCFLT = 0x0000) Figure 25.
ADuC7033 0 ADC Calibration –10 –30 As shown in detail in the top level diagrams (Figure 17 and Figure 18), the signal flow through all ADC channels can be described in simple steps. –40 1. (dB) –20 An input voltage is applied through an input buffer (and PGA in the case of the I-ADC) to the Σ-Δ modulator. The modulator output is applied to a programmable digital decimation filter. The filter output result is then averaged if chopping is used. An offset value (ADCxOF) is subtracted from the result.
ADuC7033 Self-Calibration In self (offset or gain) calibration, the ADC generates its calibration coefficient based on an internally generated 0 V in the case of self-offset calibration, and full-scale voltage in the case of self-gain calibration. It should be emphasized that ADC self-calibrations correct for offset and gain errors within the ADC. Self-calibrations cannot compensate for other external errors in the system, for example, shunt resistor tolerance/drift, external offset voltages, and so on.
ADuC7033 In summary, the simplified ADC transfer function can be described as ADCOUT Low Power Plus Mode The PGA gain is set to 512 and the K factor is 8. ⎡ V × PGA ⎤ ADCGN = ⎢ IN − ADCOF⎥ × ⎣ VREF ⎦ ADCGN NOM In low power and low power plus modes, the K factor doubles if (REG_AVDD)/2 is used as the reference. This equation is valid for the voltage/temperature channel ADC. ADC DIAGNOSTICS For the current channel ADC, The ADuC7033 features diagnostic capability on both ADCs.
ADuC7033 POWER SUPPLY SUPPORT CIRCUITS The ADuC7033 incorporates two on-chip, low dropout (LDO) regulators that are driven directly from the battery voltage to generate a 2.6 V internal supply. This 2.6 V supply is then used as the supply voltage for the ARM7 MCU and peripherals including the precision analog circuits on-chip. The digital LDO functions with two output capacitors, 2.2 μF and 0.1 μF in parallel, on REG_DVDD, whereas the analog LDO functions with an output capacitor (0.47 μF) on REG_AVDD.
ADuC7033 SYSTEM CLOCKS driven by a CD divided clock derived from the output of the PLL. By default, the CD divider is configured to divide the PLL output by two, thereby generating a core clock of 10.24 MHz. The divide factor can be modified to generate a binary weighted divider factor from 1 to 128 that can be altered dynamically by user code.
ADuC7033 The operating mode, clocking mode, and programmable clock divider are controlled using two MMRs, PLLCON and POWCON, and the status of the PLL is indicated by PLLSTA. PLLCON controls the operating mode of the clock system and POWCON controls both the core clock frequency and the power-down mode. PLLSTA indicates the presence of an oscillator on the XTAL1 pin, the PLL lock status, and the PLL interrupt.
ADuC7033 PLLCON Prewrite Key PLLKEY0 POWCON Prewrite Key POWKEY0 Name: PLLKEY0 Name: POWKEY0 Address: 0xFFFF0410 Address: 0xFFFF0404 Access: Write only Access: Write only Key: 0x000000AA Key: 0x00000001 Function: PLLCON is a keyed register that requires a 32-bit key value to be written before and after PLLCON. PLLKEY0 is the prewrite key. Function: POWCON is a keyed register that requires a 32-bit key value to be written before and after POWCON. POWKEY0 is the prewrite key.
ADuC7033 Table 46. POWCON MMR Bit Designations Bit 31 to 8 7 6 5 4 3 2 to 0 Description Reserved. Precision 131 kHz Input Enable. Cleared by the user to power-down the precision 131 kHz input enable. Set by the user to enable the precision 131 kHz input enable. The precision 131 kHz oscillator must also be enabled using HVCFG0[6]. Setting this bit increases current consumption by approximately 50 μA and should be disabled when not in use. XTAL Power-Down.
ADuC7033 User code then reads back the value of the low power oscillator calibration counter. There are three possible scenarios: • • • OSC0VAL0 = OSC0VAL1. No further action is required. OSC0VAL0 > OSC0VAL1. The low power oscillator is running slow. OSC0TRM must be decreased. OSC0VAL0 < OSC0VAL1. The low power oscillator is running fast. OSC0TRM must be increased. When the OSC0TRM is changed, the routine should be run again and the new frequency checked.
ADuC7033 OSC0STA Register OSC0VAL0 Register Name: OSC0STA Name: OSC0VAL0 Address: 0xFFFF0444 Address: 0xFFFF0448 Default Value: 0x00 Default Value: 0x0000 Access: Read access only Access: Read access only Function: This 8-bit register gives the status of the low power oscillator calibration routine. Function: This 9-bit counter is clocked from either the 131 kHz precision oscillator or the 32.768 kHz external crystal. Table 49.
ADuC7033 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 17 interrupt sources on the ADuC7033 that are controlled by the interrupt controller. Most interrupts are generated from the on-chip peripherals such as the ADC, UART, and so on. The ARM7TDMI CPU core only recognizes interrupts as one of two types: a normal interrupt request (IRQ) and a fast interrupt request (FIQ). All the interrupts can be masked separately.
ADuC7033 IRQSIG reflects the status of the different IRQ sources. If a peripheral generates an IRQ signal, the corresponding bit in the IRQSIG is set, otherwise it is cleared. The IRQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All IRQ sources can be masked in the IRQEN MMR. IRQSIG is read only. IRQEN IRQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an IRQ exception.
ADuC7033 TIMERS The ADuC7033 features five general-purpose timer/counters. Table 52. Timer Event Capture • • • • • Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Timer0, or lifetime timer Timer1 Timer2 or wake-up timer Timer3 or watchdog timer Timer4 or STI timer The five timers in their normal mode of operation can be in either free running mode or periodic mode. Timers are started by writing data to the control register of the corresponding timer (TxCON).
ADuC7033 TIMER BLOCK USER MMR INTERFACE ARM7TDMI AMBA AMBA CORE CLOCK LOW POWER OSCILLATOR T0IRQ T0 REG T0 SYNC T0 T1 REG T1 SYNC T1 T2 REG T2 SYNC T2 T3 REG T3 SYNC T3 T4 REG T4 SYNC T4 T1IRQ T2IRQ T3IRQ WDRST T4IRQ 0 GPIO 2 XTAL 4 06847-059 1 HIGH PRECISION OSCILLATOR Figure 32. Timer Block Diagram SYNCHRONIZER FLIP-FLOPS CORE CLOCK (FCORE) DOMAIN SYNCHRONIZED SIGNAL TARGET_CLOCK TIMER 2 LOW POWER CLOCK DOMAIN 06847-060 UNSYNCHRONIZED SIGNAL Figure 33.
ADuC7033 Starting Timer2 When starting Timer2, it is recommended to first load Timer2 with the required TxLD value. Next, start the timer by setting the T2CON bits as required. This enables the timer but only once the T2CON bits have been latched internally in the Timer2 clock domain.
ADuC7033 • TIMER0—LIFETIME TIMER Timer0 is a general-purpose, 48-bit count up, or a 16-bit count up/down timer with a programmable prescaler. Timer0 can be clocked from either the core clock or the low power 32.768 kHz oscillator with a prescaler of 1, 16, 256, or 32,768. This gives a minimum resolution of 48.83 ns when the core is operating at 20.48 MHz with a prescaler of 1. In 48-bit mode, Timer0 counts up from zero. The current counter value can be read from T0VAL0 and T0VAL1.
ADuC7033 Timer0 Control Register Name: T0CON Address: 0xFFFF030C Default Value: 0x00000000 Access: Read/write Function: The 32-bit MMR configures the mode of operation for Timer0. Table 53. T0CON MMR Bit Designations Bit 31 to 18 17 16 to 12 11 10 to 9 8 7 6 5 4 3 to 0 Description Reserved. Event Select Bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. Event Select Range (0 to 31). The events are as described in Table 52. Reserved.
ADuC7033 Timer0 Load Registers Timer0 Clear Register Name: T0LD Name: T0CLRI Address: 0xFFFF0300 Address: 0xFFFF0310 Default Value: 0x0000 Access: Write only Function: Access: Read/write This 16-bit, write only MMR is written (with any value) by user code to clear the interrupt. Function: T0LD0 is the 16-bit register holding the 16-bit value that is loaded into the counter. Available in 16-bit mode only. Rev.
ADuC7033 TIMER1 Timer1 Load Registers Timer1 is a 32-bit general-purpose timer, count-down or countup, with a programmable prescaler. The prescaler source can be the low power 32.768 kHz oscillator, the core clock, or from one of two external GPIOs. This source can be scaled by a factor of 1, 16, 256, or 32,768. This gives a minimum resolution of 48.83 ns when operating at CD zero, the core is operating at 20.48 MHz, and with a prescaler of 1 (ignoring the external GPIOs).
ADuC7033 Timer1 Capture Register Name: T1CAP Address: 0xFFFF0330 Default Value: 0x00000000 Access: Read only Function: This 32-bit register holds the 32-bit value captured by an enabled IRQ event. Timer1 Control Register Name: T1CON Address: 0xFFFF0328 Default Value: 0x01000000 Access: Read/write Function: This 32-bit MMR configures the mode of operation of Timer1. Table 54.
ADuC7033 Bit 5 to 4 3 to 0 Description Format. 00 = binary (default). 01 = reserved. 10 = hours:minutes:seconds:hundredths (23 hours to 0 hours). 11 = hours:minutes:seconds:hundredths (255 hours to 0 hours). Prescaler. 0000 = source clock/1 (default). 0100 = source clock/16. 1000 = source clock/256. 1111 = source clock/32,768. Timer2 Load Registers TIMER2 OR WAKE-UP TIMER Timer2 is a 32-bit wake-up timer, count-down or count-up, with a programmable prescaler.
ADuC7033 Timer2 Control Register Name: T2CON Address: 0xFFFF0348 Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR configures the mode of operation of Timer2. Table 55. T2CON MMR Bit Designations Bit 15 to 11 10 to 9 8 7 6 5 to 4 3 to 0 Description Reserved. Clock Source Select. 00 = core clock (default). 01 = low power (32.768 kHz) oscillator. 10 = external (32.768 kHz) watch crystal. 11 = precision (32.768 kHz) oscillator. Count Up. Set by user for Timer2 to count up.
ADuC7033 TIMER3 OR WATCHDOG TIMER 16-BIT LOAD PRESCALER 1, 16, 256 16-BIT UP/DOWN COUNTER WATCHDOG RESET TIMER3 IRQ 06847-033 LOW POWER 32.768kHz TIMER3 VALUE Figure 37. Timer3 Block Diagram Timer3 has two modes of operation, normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. When enabled, it requires periodic servicing to prevent it from forcing a reset of the processor. Timer3 Interface The Timer3 interface consists of four MMRs.
ADuC7033 Timer3 Control Register Name: T3CON Address: 0xFFFF0368 Default Value: 0x0000 Access: Read/write Function: The 16-bit MMR configures the mode of operation of Timer3 as described in detail in Table 56. Table 56. T3CON MMR Bit Designations Bit 15 to 9 8 7 6 5 4 3 to 2 1 0 Description Reserved. These bits are reserved and should be written as 0 by user code. Count Up/Count Down Enable. Set by user code to configure Timer3 to count up.
ADuC7033 TIMER4 OR STI TIMER Timer4 Value Register Timer4 is a general-purpose, 16-bit, count up/count down timer with a programmable prescaler. Timer4 can be clocked from the core clock or the low power 32.768 kHz oscillator with a prescaler of 1, 16, 256, or 32,768. Name: T4VAL Address: 0xFFFF0384 Default Value: 0xFFFF Access: Read only Function: T4VAL is a 16-bit register that holds the current value of Timer4.
ADuC7033 Table 57. T4CON MMR Bit Designations Bit 31 to 18 17 16 to 12 11 to 10 9 8 7 6 5 to 4 3 to 0 Description Reserved. Event Select Bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. Event Select Range, 0 to 31. The events are described in Table 52. Reserved. Clock Select. 0 = core clock (default). 1 = low power (32.768 kHz) oscillator. Count Up. Set by user for Timer4 to count up. Cleared by user for Timer4 to count down (default).
ADuC7033 GENERAL-PURPOSE INPUT/OUTPUT The ADuC7033 features nine general-purpose bidirectional input/output (GPIO) pins. In general, many of the GPIO pins have multiple functions that can be configured by user code. By default, the GPIO pins are configured in GPIO mode. All GPIO pins have an internal pull-up resistor with a sink capability of 0.8 mA and a source capability of 0.1 mA.
ADuC7033 Table 58. External GPIO Pin to Internal Port Signal Assignments Port Port0 GPIO Pin GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 Port1 GPIO_5 GPIO_6 Port2 GPIO_7 GPIO_8 GPIO_112 GPIO_122 GPIO_131 Port Signal P0.0 IRQ0 SS P0.1 SCLK P0.2 MISO P0.3 MOSI P0.4 ECLK P0.51 P0.61 P1.0 IRQ1 RxD P1.1 TxD Port2.0 IRQ4 LIN output pin P2.1 IRQ5 LIN input pin P2.42 P2.52 P2.61 Functionality (Defined by GPxCON) General-Purpose I/O. External Interrupt Request 0. Slave Select I/O for SPI. General-Purpose I/O.
ADuC7033 GPIO Port0 Control Register Name: GP0CON Address: 0xFFFF0D00 Default Value: 0x11100000 Access: Read/write Function: The 32-bit MMR selects the pin function for each Port0 pin. Table 59. GP0CON MMR Bit Designations Bit 31 to 29 28 27 to 25 24 23 to 21 20 19 to 17 16 15 to 13 12 11 to 9 8 7 to 5 4 3 to 1 0 Description Reserved. These bits are reserved and should be written as 0 by user code. Reserved. This bit is reserved and should be written as 1 by user code. Reserved.
ADuC7033 GPIO Port1 Control Register Name: GP1CON Address: 0xFFFF0D04 Default Value: 0x10000000 Access: Read/write Function: The 32-bit MMR selects the pin function for each Port1 pin. Table 60. GP1CON MMR Bit Designations Bit 31 to 5 4 3 to 1 0 Description Reserved. These bits are reserved and should be written as 0 by user code. GPIO_6 Function Select Bit. Cleared by user code to 0 to configure the GPIO_6 pin as a general-purpose I/O (GPIO) pin.
ADuC7033 Bit 4 3 to 1 0 Description GPIO_8 Function Select Bit. Cleared by user code to 0 to configure the GPIO_8 pin as a general-purpose I/O (GPIO) pin. Set by user code to 1 to route the LIN/BSD input data to the GPIO_8 pin. This mode can be used to drive the LIN transceiver interface as a standalone component without any interaction from MCU or UART. Reserved. These bits are reserved and should be written as 0 by user code. GPIO_7 Function Select Bit.
ADuC7033 GPIO Port0 Data Register Name: GP0DAT Address: 0xFFFF0D20 Default Value: 0x000000XX Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port0 (see Table 58). This register also sets the output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs. Table 62. GP0DAT MMR Bit Designations Bit 31 to 29 28 27 26 25 24 23 to 21 20 19 18 17 16 15 to 5 4 3 2 1 0 Description Reserved.
ADuC7033 GPIO Port1 Data Register Name: GP1DAT Address: 0xFFFF0D30 Default Value: 0x000000XX Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port1 (see Table 58). This register also sets the output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs. Table 63. GP1DAT MMR Bit Designations Bit 31 to 26 25 24 23 to 18 17 16 15 to 2 1 0 Description Reserved.
ADuC7033 GPIO Port2 Data Register Name: GP2DAT Address: 0xFFFF0D40 Default Value: 0x000000XX Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port2 (see Table 58). This register also sets the output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs. Table 64. GP2DAT MMR Bit Designations Bit 31 30 29 28 27 to 26 25 24 23 22 21 20 to 18 17 16 15 to 7 6 5 4 3 to 2 1 0 Description Reserved.
ADuC7033 GPIO Port0 Set Register Name: GP0SET Address: 0xFFFF0D24 Access: Write only Function: This 32-bit MMR allows user code to individually bit address external GPIO pins to set them high only. User code can accomplish this using the GP0SET MMR without having to modify or maintain the status of any other GPIO pins (as user code requires when using GP0DAT). Table 65. GP0SET MMR Bit Designations Bit 31 to 21 20 19 18 17 16 15 to 0 Description Reserved.
ADuC7033 GPIO Port2 Set Register Name: GP2SET Address: 0xFFFF0D44 Access: Write only Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to set them high only. User code can accomplish this using the GP2SET MMR without having to modify or maintain the status of any other GPIO pins (as user code requires when using GP2DAT). Table 67. GP2SET MMR Bit Designations Bit 31 to 23 22 21 20 to 18 17 16 15 to 0 Description Reserved.
ADuC7033 GPIO Port1 Clear Register Name: GP1CLR Address: 0xFFFF0D38 Access: Write only Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to clear them low only. User code can accomplish this using the GP1CLR MMR without having to modify or maintain the status of any other GPIO pins (as user code requires when using GP1DAT). Table 69. GP1CLR MMR Bit Designations Bit 31 to 18 17 16 15 to 0 Description Reserved.
ADuC7033 HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE The ADuC7033 integrates a number of high voltage circuit functions that are controlled and monitored through a registered interface consisting of two MMRs, namely, HVCON and HVDAT. The HVCON register acts as a command byte interpreter allowing the microcontroller to indirectly read or write 8-bit data (the value in HVDAT) from or to one of four high voltage status or configuration registers.
ADuC7033 High Voltage Interface Control Register Name: HVCON Address: 0xFFFF0804 Default Value: Updated by kernel Access: Read/write Function: This 8-bit register acts as a command byte interpreter for the high voltage control interface. Bytes written to this register are interpreted as read or write commands to a set of four indirect registers related to the high voltage circuits. The HVDAT register is used to store data to be written to, or read back from, the indirect registers. Table 71.
ADuC7033 High Voltage Data Register Name: HVDAT Address: 0xFFFF080C Default Value: Updated by kernel Access: Read/write Function: HVDAT is a 12-bit register that is used to hold data to be written indirectly to, and read indirectly from, the following high voltage interface registers. Table 73. HVDAT MMR Bit Designations Bit 11 to 8 7 to 0 Description Command with which High Voltage Data HVDAT[7:0] is associated. These bits are read only and should be written as zeros.
ADuC7033 High Voltage Configuration0 Register Name: HVCFG0 Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the function of high voltage circuits on the ADuC7033. This register is not an MMR and does not appear in the MMR memory map. It is accessed via the HVCON registered interface.
ADuC7033 High Voltage Configuration1 Register Name: HVCFG1 Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the function of high voltage circuits on the ADuC7033. This register is not an MMR and does not appear in the MMR memory map. It is accessed via the HVCON registered interface; data to be written to this register is loaded through HVDAT and data is read back from this register using HVDAT.
ADuC7033 High Voltage Monitor Register Name: HVMON Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read only Function: This 8-bit, read only register reflects the current status of enabled high voltage related circuits and functions on the ADuC7033. This register is not an MMR and does not appear in the MMR memory map. It is accessed via the HVCON registered interface, and data is read back from this register via HVDAT. Table 76.
ADuC7033 High Voltage Status Register Name: HVSTA Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read only, this register should only be read on a high voltage interrupt Function: This 8-bit, read-only register reflects a change of state for all the corresponding bits in the HVMON register. This register is not an MMR and does not appear in the MMR memory map.
ADuC7033 By default, the monoflop is enabled and disables the wake-up driver after 1.3 seconds. It is possible to disable the monoflop through HVCFG1[1]. If the wake-up monoflop is disabled, then the wake-up driver should be disabled after 1.3 seconds. WAKE-UP (WU) PIN The wake-up (WU) pin is a high voltage GPIO controlled through HVCON and HVDAT. WU Pin Circuit Description The WU pin also features a short-circuit detection feature.
ADuC7033 HANDLING INTERRUPTS FROM THE HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE An interrupt controller is also integrated with the high voltage circuits. If enabled through IRQEN[16], one of six high voltage sources can assert the high voltage interrupt (IRQ3) signal and interrupt the MCU core.
ADuC7033 UART SERIAL INTERFACE The ADuC7033 features a 16,450-compatible UART. The UART is a full-duplex, universal, asynchronous receiver/transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device, and parallel-to-serial conversion on data characters received from the ARM7TDMI. The UART features a fractional divider that facilitates high accuracy baud rate generation and a network addressable mode.
ADuC7033 UART Tx Register UART Divisor Latch Register 0 Name: COMTX Name: COMDIV0 Address: 0xFFFF0700 Address: 0xFFFF0700 Access: Write only 0x00 Function: Write to this 8-bit register to transmit data using the UART. Default Value: Access: Read/write Function: This 8-bit register contains the least significant byte of the divisor latch that controls the baud rate at which the UART operates.
ADuC7033 UART Control Register 0 Name: COMCON0 Address: 0xFFFF070C Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the operation of the UART in conjunction with COMCON1. Table 81. COMCON0 MMR Bit Designations Bit 7 Name DLAB 6 BRK 5 SP 4 EPS 3 PEN 2 STOP 1 to 0 WLS Description Divisor Latch Access. Set by user to enable access to COMDIV0 and COMDIV1 registers.
ADuC7033 UART Control Register 1 Name: COMCON1 Address: 0xFFFF0710 Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the operation of the UART in conjunction with COMCON0. Table 82. COMCON1 MMR Bit Designations Bit 7 to 6 5 4 3 to 0 Name LOOPBACK Description UART Input Mux. 00 = RxD driven by LIN input; required for LIN communications using the LIN pin. 01 = reserved. 10 = RxD driven by GP5; required for serial communications using GPIO_5 pin (RxD). 11 = reserved.
ADuC7033 UART Interrupt Enable Register 0 Name: COMIEN0 Address: 0xFFFF0704 Default Value: 0x00 Access: Read/write Function: The 8-bit register enables and disables the individual UART interrupt sources. Table 84. COMIEN0 MMR Bit Designations Bit 7 to 4 3 2 Name 1 ETBEI 0 ERBFI EDSSI ELSI Description Reserved. Not used. Reserved. This bit should be written as 0. RxD Status Interrupt Enable Bit.
ADuC7033 UART Fractional Divider Register Name: COMDIV2 Address: 0xFFFF072C Default Value: 0x0000 Access: Read/write Function: This 16-bit register controls the operation of the fractional divider for the ADuC7033. Table 86. COMDIV2 MMR Bit Designations Bit 15 Name FBEN 14 to 13 12 to 11 FBM[1:0] 10 to 0 FBN[10:0] Description Fractional Baud Rate Generator Enable Bit. Set by the user to enable the fractional baud rate generator.
ADuC7033 SERIAL PERIPHERAL INTERFACE The ADuC7033 features a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industry standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, that is, full duplex. The SPI interface is only operational with core clock divider bits (POWCON[2:0] = 0 or 1). The SPI port can be configured for master or slave operation and consists of four pins that are multiplexed with four GPIOs.
ADuC7033 SPI Control Register Name: SPICON Address: 0xFFFF0A10 Default Value: 0x0000 Access: Read/write Function: The 16-bit MMR configures the serial peripheral interface. Table 89. SPICON MMR Bit Designations Bit 15 to 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description Reserved. Continuous Transfer Enable. Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the SPITX register.
ADuC7033 SPI Status Register SPI Receive Register Name: SPISTA Name: SPIRX Address: 0xFFFF0A00 Address: 0xFFFF0A04 Default Value: 0x00 Default Value: 0x00 Access: Read only Access: Read only Function: The 8-bit MMR represents the current status of the serial peripheral interface. Function: This 8-bit MMR contains the data received using the serial peripheral interface. SPI Transmit Register Table 90. SPISTA MMR Bit Designations Bit 7 to 6 5 4 3 2 1 0 Description Reserved.
ADuC7033 SERIAL TEST INTERFACE STI BYTE1 PARITY BIT START BIT STI BYTE2 PAIRTY BIT WITH 2 STOP BITS 06847-039 STI BYTE0 Figure 43. Serial ADC Test Interface Example, Three-Byte Transmission The ADuC7033 incorporates single pin, serial test interface (STI) ports that can be used for end-customer evaluation or diagnostics on finished production units. The STI port transmits from one byte to six bytes of data in 12-bit packets.
ADuC7033 Serial Test Interface Data 2 Register Serial Test Interface Control Register Name: STIDAT1 Name: STICON Address: 0xFFFF0894 Address: 0xFFFF0884 Default Value: 0x0000 Default Value: 0x0000 Access: Read/write Access: Function: The STIDAT2 MMR is a 16-bit register that holds the fifth and sixth data bytes that are to be transmitted on the STI pin when the STI port is enabled. The fifth byte to be transmitted occupies Bits[7:0] and the sixth byte occupies Bits[15:8].
ADuC7033 Table 91. STICON MMR Bit Designations Bit 16 to 9 8 to 5 4 to 2 1 0 Description Reserved. These bits are reserved for future use and should be written as 0 by user code. State Bits, Read Only. If the interface is in the middle of a transmission, these bits are not 0. Number of Bytes to Transmit. These bits select the number of bytes to be transmitted. User code must subsequently write the bytes to be transmitted into the STIDAT0, STIDAT1, and STIDAT2 MMRs. 000 = 1-byte transmission.
ADuC7033 An example code segment configuring the STI port to transmit five bytes and then to transmit two bytes follows: T4LD = 267; T4CON = 0xC0; // Timer4 Reload Value // Enable T4, selecting core clock in periodic mode STIKEY0 = 07; STICON = 0x11; STIKEY1 = 0xb9; // STICON start write sequence // Enable and transmit 5 bytes // STICON complete write STIDAT0 = 0xAABB; // 5 bytes for STIDAT1 = 0xCCDD; STIDAT2 = 0xFF; // Transmission while(STICON != 0x09) // Wait for transmission to complete {} STI
ADuC7033 LIN (LOCAL INTERCONNECT NETWORK) INTERFACE The ADuC7033 features high voltage physical interfaces between the ARM7 MCU core and an external LIN bus. The LIN interface operates as a slave only interface, operating from 1 kBaud to 20 kBaud, and it is compatible with the LIN 2.0 standard. The pull-up resistor required for a slave node is onchip, reducing the need for external circuitry.
ADuC7033 LIN Hardware Synchronization Status Register Name: LHSSTA Address: 0xFFFF0780 Default Value: 0x00 Access: Read only Function: The LHS status register is a 32-bit register whose bits reflect the current operating status of the ADuC7033 LIN interface. Table 93. LHSSTA MMR Bit Designations Bit 31 to 7 6 5 4 3 2 1 0 Description Reserved. These read-only bits are reserved for future use. Rising Edge Detected (BSD Mode Only).
ADuC7033 LIN Hardware Synchronization Control Register 0 Name: LHSCON0 Address: 0xFFFF0784 Default Value: 0x0000 Access: Read/write Function: The LHS control register is a 32-bit register that, in conjunction with the LHSCON1 register, is used to configure the LIN mode of operation. Table 94. LHSCON0 MMR Bit Designations Bit 31 to 13 12 11 10 9 8 Description Reserved. These bits are reserved for future use and should be written as 0 by user software. Rising Edge Detected Interrupt Disable.
ADuC7033 Bit 7 6 5 4 3 2 1 0 Description Sync Timer Stop Edge Type Bit. Cleared to 0 by user code to stop the sync timer on the falling edge count configured through the LHSCON1[7:4] register. Set to 1 by user code to stop the sync timer on the rising edge count configured through the LHSCON1[7:4] register. Mode of Operation Bit. Cleared to 0 by user code to select LIN mode of operation. Set to 1 by user code to select BSD mode of operation. Enable Compare Interrupt Bit.
ADuC7033 LIN Hardware Synchronization Control Register 1 Name: LHSCON1 Address: 0xFFFF078C Default Value: 0x32 Access: Read/write Function: The LHS control register is a 32-bit register that, in conjunction with the LHSCON0 register, is used to configure the LIN mode of operation. Table 95. LHSCON1 MMR Bit Designations Bit 31 to 8 7 to 4 3 to 0 Description Reserved. These bits are reserved for future use and should be written as 0 by user software. LIN Stop Edge Count.
ADuC7033 dependent on the revision of LIN for which the system is designed. LIN HARDWARE INTERFACE LIN Frame Protocol The LIN frame protocol is broken into four main categories: break symbol, sync byte, protected identifier, and data bytes. The format of the frame header, break, synchronization byte, and protected identifier are shown in Figure 4 .
ADuC7033 >1TBIT 8TBIT 2TBIT 2TBIT STA S0 BREAK S1 S2 2TBIT S3 S4 2TBIT S5 S6 S7 STO SYNC PROTECTED ID 06847-042 > = 14TBIT 13TBIT Figure 46. LIN Interface Timing TBREAK > 13TBIT BREAK DELIMIT 06847-043 START BIT Figure 47. LIN Break Field START BIT STOP BIT 06847-044 TBIT Figure 48. LIN Sync Byte Field ID0 ID1 ID2 ID3 ID4 ID5 P0 P1 STOP BIT 06847-045 START BIT BIT6 BIT7 STOP BIT 06847-046 TBIT Figure 49.
ADuC7033 Example LIN Hardware Synchronization Routine Consider the following C-Source Code LIN initialization routine.
ADuC7033 while((GP2DAT & 0x10 ) == 0 ) {} LHSCON0 = 0x4; // // // // // IRQEN = 0x800; LHSVAL1 RESET AND STARTS COUNTING BREAK COMPARE INTERRUPT GENERATED LHSVAL0 STARTS COUNTING Wait until LIN Bus returns high Enable LHS to detect Break Condition Ungate RX Line Disable all Interrupts except Break Compare Interrupt Enable UART Interrupt The UART is now configured and ready to be used for LIN LHSVAL0 STOPS UART CONFIGURED BEGIN COUNTING.
ADuC7033 BIT SERIAL DEVICE (BSD) INTERFACE LHS INTERRUPT LOGIC LHS INTERRUPT IRQEN[7] ADuC7033 LHS HARDWARE 5MHz LHSVAL0 131kHz LHSVAL1 FOUR LIN INTERRUPT SOURCES BREAK LHSSTA[0] START LHSSTA[1] STOP LHSSTA[2] BREAK ERROR LHSSTA[4] VDD VDD LIN ENABLE (INTERNAL PULL-UP) HVCFG0[5] INPUT VOLTAGE THRESHOLD REFERENCE RxD ENABLE LHSCON0[8] EXTERNAL LIN PIN RxD ADuC7033 MASTER ECU PULL-UP CLOAD OVER VOLTAGE PROTECTION LIN MODE HVCFG0[1:0] UART MASTER ECU PROTECTION DIODE SCR TxD BPF OUTPUT DISA
ADuC7033 Detailed bit definitions for most of these MMRs have been listed previously. In addition to the registers described in the LIN MMR Description section, LHSCAP and LHSCMP are registers that are required for the operation of the BSD interface. Details of these registers follow. The slave then transmits the data bytes, P2, and the acknowledge in the following sequence: 1. 2. LIN Hardware Synchronization Capture Register 3. 4. 5. 6. 7.
ADuC7033 BSD DATA RECEPTION BUS RELEASED BY SLAVE AFTER t0 t0 06847-051 BUS HELD LOW BY SLAVE RELEASED BY MASTER tSYNC To receive data, the LIN/BSD peripheral must first be configured in BSD mode where LHSCON[6] = 1. In this mode, LHSCON0[8] should be set to ensure the LHS break timer (see LHSVAL1 in the LIN Hardware Break Timer1 Register section) generates an interrupt on the rising edge of the BSD bus. Figure 55.
ADuC7033 2 LHSVAL0 LOADED INTO LHSCAP HERE WAKE-UP FROM BSD INTERFACE 3 SOFTWARE ASSERTS BSD LOW HERE BSD ‘0’ PERIOD BSD ‘1’ PERIOD 06847-054 1 MASTER DRIVES BSD BUS LOW 4 LHSCMP = LHSVAL0 INTERRUPT GENERATED HERE 5 SOFTWARE DEASSERTS BSD HIGH HERE The MCU core can be woken up from power-down via the BSD physical interface. Before entering power-down mode, user code should enable the start condition interrupt (LHSCON0[3]).
ADuC7033 PART IDENTIFICATION Two registers mapped into the MMR space are intended to allow user code to identify and trace manufacturing lot ID information, part ID number, silicon mask revision, and kernel revision. This information is contained in the SYSSER0 and SYSSER1 MMRs. See Table 99 and Table 100 for details. For full traceability, the part assembly lot number, SYSSER0, and module number need to be recorded. The lot number is part of the branding on the package as shown Table 98. Table 98.
ADuC7033 System Serial ID Register 1 Name: SYSSER1 Address: 0xFFFF023C Default Value: 0x00000000 (updated by kernel at power-on) Access: Read/write Function: At power-on, this 32-bit register holds the values of the part ID number, silicon mask revision number, and kernel revision number (bottom die only) as detailed in Table 100. Table 100. SYSSER1 MMR Bit Designations Bit 31 to 28 27 to 20 19 to 16 15 to 0 Description Silicon Mask Revision ID.
ADuC7033 System Identification FEE0ADR Name: FEE0ADR Address: 0xFFFF0E10 Default Value: Nonzero Access: Read/write Function: This 16-bit register dictates the address upon which any Flash/EE command executed via FEE0CON acts. Note: This MMR is also used to identify the ADuC703x family member and prerelease silicon revision. Table 101.
ADuC7033 SCHEMATIC This example schematic represents a basic functional circuit implementation. Additional components need to be added to ensure that the system meets any EMC and other overvoltage/overcurrent compliance requirements. GROUND CONNECTED TO THE NEGATIVE TERMINAL OF THE BATTERY 06847-055 Figure 59. Schematic Rev.
ADuC7033 OUTLINE DIMENSIONS 0.75 0.60 0.45 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY SEATING PLANE (PINS DOWN) 25 12 13 VIEW A 0.50 BSC LEAD PITCH VIEW A 24 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC 051706-A 0.15 0.05 7.20 7.00 SQ 6.80 TOP VIEW 1.45 1.40 1.35 Figure 60.
ADuC7033 NOTES Rev.
ADuC7033 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06847-0-10/10(B) Rev.
