Datasheet

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 31 of 104
ADUC7028
A
8
7 6
5 4
3
2 1
B
C
D
E
F
G
H
BOTTOM VIEW
(Not to Scale)
04955-086
Figure 26. 64-Ball CSP_BGA Pin Configuration (ADuC7028)
Table 14. Pin Function Descriptions (ADuC7028)
Ball No. Mnemonic Description
A1 ADC3/CMP1 Single-Ended or Differential Analog Input 3/Comparator Negative Input.
A2 DACV
DD
3.3 V Power Supply for the DACs. Must be connected to AV
DD
.
A3 AV
DD
3.3 V Analog Power.
A4 AGND Analog Ground. Ground reference point for the analog circuitry.
A5 DACGND Ground for the DAC. Typically connected to AGND.
A6 P4.2/PLAO[10] General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10.
A7 P1.1/SPM1/PLAI[1] Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable
Logic Array Input Element 1.
A8 P1.2/SPM2/PLAI[2] Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
B1 ADC4 Single-Ended or Differential Analog Input 4.
B2 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input.
B3 ADC1 Single-Ended or Differential Analog Input 1.
B4 DAC
REF
External Voltage Reference for the DACs. Range: DACGND to DACV
DD
.
B5 V
REF
2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor when using the
internal reference.
B6 P1.0/T1/SPM0/PLAI[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/
Programmable Logic Array Input Element 0.
B7 P1.4/SPM4/PLAI[4]/IRQ2 Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable
Logic Array Input Element 4/External Interrupt Request 2, Active High.
B8 P1.3/SPM3/PLAI[3] Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
C1 ADC6 Single-Ended or Differential Analog Input 6.
C2 ADC5 Single-Ended or Differential Analog Input 5.
C3 ADC0 Single-Ended or Differential Analog Input 0.
C4 P4.5/PLAO[13] General-Purpose Input and Output Port 4.5/Programmable Logic Array Output Element 13.
C5 P4.3/PLAO[11] General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11.
C6 P4.0/PLAO[8] General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8.
C7 P4.1/PLAO[9] General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9.
C8 IOGND Ground for GPIO (see Table 78). Typically connected to DGND.
D1 ADCNEG Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be
connected to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
D2 GND
REF
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
D3 ADC7 Single-Ended or Differential Analog Input 7.
D4 P4.4/PLAO[12] General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12.
D5 P3.6/PWM
TRIP
/PLAI[14] General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array
Input Element 14.
D6
P1.7/SPM7/PLAO[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable
Logic Array Output Element 0.