Datasheet

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 65 of 104
Output Control Unit
The operation of the output control unit is controlled by the
9-bit read/write PWMEN register. This register controls two
distinct features of the output control unit that are directly
useful in the control of electronic counter measures (ECM) or
binary decimal counter measures (BDCM). The PWMEN
register contains three crossover bits, one for each pair of PWM
outputs. Setting Bit 8 of the PWMEN register enables the
crossover mode for the 0H/0L pair of PWM signals, setting
Bit 7 enables crossover on the 1H/1L pair of PWM signals, and
setting Bit 6 enables crossover on the 2H/2L pair of PWM
signals. If crossover mode is enabled for any pair of PWM
signals, the high-side PWM signal from the timing unit (0H, for
example) is diverted to the associated low-side output of the
output control unit so that the signal ultimately appears at the
PWM0
L
pin. Of course, the corresponding low-side output of
the timing unit is also diverted to the complementary high-side
output of the output control unit so that the signal appears at
the PWM0
H
pin. Following a reset, the three crossover bits are
cleared, and the crossover mode is disabled on all three pairs of
PWM signals. The PWMEN register also contains six bits (Bit 0
to Bit 5) that can be used to individually enable or disable each
of the six PWM outputs. If the associated bit of the PWMEN
register is set, the corresponding PWM output is disabled
regardless of the corresponding value of the duty cycle register.
This PWM output signal remains in the off state as long as the
corresponding enable/disable bit of the PWMEN register is set.
The implementation of this output enable function is imple-
mented after the crossover function.
Following a reset, all six enable bits of the PWMEN register are
cleared, and all PWM outputs are enabled by default. In a manner
identical to the duty cycle registers, the PWMEN is latched on
the rising edge of the PWMSYNC signal. As a result, changes to
this register become effective only at the start of each PWM cycle
in single update mode. In double update mode, the PWMEN
register can also be updated at the midpoint of the PWM cycle.
In the control of an ECM, only two inverter legs are switched at
any time, and often the high-side device in one leg must be
switched on at the same time as the low-side driver in a second
leg. Therefore, by programming identical duty cycle values for
two PWM channels (for example, PWMCH0 = PWMCH1) and
setting Bit 7 of the PWMEN register to cross over the 1H/1L
pair of PWM signals, it is possible to turn on the high-side
switch of Phase A and the low-side switch of Phase B at the
same time. In the control of ECM, it is usual for the third
inverter leg (Phase C in this example) to be disabled for a
number of PWM cycles. This function is implemented by
disabling both the 2H and 2L PWM outputs by setting Bit 0
and Bit 1 of the PWMEN register.
This situation is illustrated in Figure 71, where it can be seen
that both the 0H and 1L signals are identical because
PWMCH0 = PWMCH1 and the crossover bit for Phase B is set.
04955-030
PWMCH0 =
PWMCH1
0H
0L
1H
1L
2H
2L
PWMCH0 =
PWMCH1
2 × PWMDAT12 × PWMDAT1
PWMDAT0 PWMDAT0
Figure 71. Active Low PWM Signals Suitable for ECM Control,
PWMCH0 = PWMCH1, Crossover 1H/1L Pair and Disable
0L, 1H, 2H, and 2L Outputs in Single Update Mode.
In addition, the other four signals (0L, 1H, 2H, and 2L) have
been disabled by setting the appropriate enable/disable bits of
the PWMEN register. In Figure 71, the appropriate value for
the PWMEN register is 0x00A7. In normal ECM operation,
each inverter leg is disabled for certain periods of time to
change the PWMEN register based on the position of the rotor
shaft (motor commutation).
Gate Drive Unit
The gate drive unit of the PWM controller adds features that
simplify the design of isolated gate-drive circuits for PWM
inverters. If a transformer-coupled, power device, gate-drive
amplifier is used, the active PWM signal must be chopped at a
high frequency. The 16-bit read/write PWMCFG register
programs this high frequency chopping mode. The chopped
active PWM signals can be required for the high-side drivers
only, the low-side drivers only, or both the high-side and low-
side switches. Therefore, independent control of this mode for
both high-side and low-side switches is included with two
separate control bits in the PWMCFG register.
Typical PWM output signals with high frequency chopping
enabled on both high-side and low-side signals are shown in
Figure 72. Chopping of the high-side PWM outputs (0H, 1H,
and 2H) is enabled by setting Bit 8 of the PWMCFG register.
Chopping of the low-side PWM outputs (0L, 1L, and 2L) is
enabled by setting Bit 9 of the PWMCFG register. The high
chopping frequency is controlled by the 8-bit word (GDCLK)
placed in Bit 0 to Bit 7 of the PWMCFG register. The period of
this high frequency carrier is
t
CHOP
= (4 × (GDCLK + 1)) × t
CORE
The chopping frequency is, therefore, an integral subdivision of
the MicroConverter core frequency
f
CHOP
= f
CORE
/(4 × (GDCLK + 1))