Datasheet
Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 95 of 104
POWER-ON RESET OPERATION
An internal power-on reset (POR) is implemented on the
ADuC7019/20/21/22/24/25/26/27/28/29. For LV
DD
below 2.35 V
typical, the internal POR holds the part in reset. As LV
DD
rises
above 2.35 V, an internal timer times out for, typically, 128 ms
before the part is released from reset. The user must ensure that
the power supply IOV
DD
reaches a stable 2.7 V minimum level
by this time. Likewise, on power-down, the internal POR holds
the part in reset until LV
DD
drops below 2.35 V.
Figure 94 illustrates the operation of the internal POR in detail.
TYPICAL SYSTEM CONFIGURATION
A typical ADuC7020 configuration is shown in Figure 95. It
summarizes some of the hardware considerations discussed in
the previous sections. The bottom of the CSP package has an
exposed pad that must be soldered to a metal plate on the board
for mechanical reasons. The metal plate of the board can be
connected to ground.
IO
V
DD
3.3
V
2.6V
2.35V TYP2.35V TYP
128ms TYP
LV
DD
POR
MRST
0.12ms TYP
04955-050
Figure 94. Internal Power-On Reset Operation
NOT CONNECTED IN THIS EXAMPLE
30
29
28
27
26
25
XCLKI
24
XCLKO
23
22
21
1
2
3
GND
REF
4
DAC0
5
6
7
8
TMS
9
TDI
10
P0.0
40 39 38
ADC0
37
AV
DD
36
AGND
35
V
REF
34 33
P1.0
32
P1.1
31
11 12 13
TDO
TCK
14
IOGND
15
IOV
DD
16
LV
DD
DGND
17 18
TRST
19
RST
20
DV
DD
1kΩ
10Ω
ADuC7020
0.01µF
+
–
AV
DD
0.47µF
TDO
TCK
TMS
TDI
TRST
JTAG CONNECTOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DV
DD
DV
DD
100kΩ
100kΩ
100kΩ
DV
DD
DV
DD
32.768kHz
0.47µF
1kΩ
0.1µF10µF10µF
1.5Ω
270Ω
DV
DD
AV
DD
ADP3333-3.3
INOUT
SDGND
1
C1+
2
V+
3
C1–
4
C2+
5
C2–
6
V–
7
T2
OUT
8
R2
IN
ADM3202
RS232 INTERFACE*
* EXTERNAL UART TRANSCEIVER INTEGRATED IN SYSTEM OR AS
PART OF AN EXTERNAL DONGLE AS DESCRIBED IN uC006.
STANDARD D-TYPE
SERIAL COMMS
CONNECTOR TO
PC HOST
16
V
CC
15
GND
14
T1
OUT
13
R1
IN
12
R1
OUT
11
T1
IN
10
T2
IN
9
R2
OUT
1
2
3
4
5
6
7
8
9
04955-051
Figure 95. Typical System Configuration