Datasheet

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 75 of 104
SPI Registers
The following MMR registers are used to control the SPI
interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
Table 119. SPISTA Register
Name Address Default Value Access
SPISTA
0xFFFF0A00
0x00
R
SPISTA is an 8-bit read-only status register. Only Bit 1 or Bit 4
of this register generates an interrupt. Bit 6 of the SPICON
register determines which bit generates the interrupt.
Table 120. SPISTA MMR Bit Descriptions
Bit Description
7:6 Reserved.
5 SPIRX data register overflow status bit. Set if SPIRX is
overflowing. Cleared by reading the SPIRX register.
4 SPIRX data register IRQ. Set automatically if Bit 3 or Bit 5
is set. Cleared by reading the SPIRX register.
3 SPIRX data register full status bit. Set automatically if a
valid data is present in the SPIRX register. Cleared by
reading the SPIRX register.
2 SPITX data register underflow status bit. Set auto-
matically if SPITX is underflowing. Cleared by writing in
the SPITX register.
1 SPITX data register IRQ. Set automatically if Bit 0 is clear
or Bit 2 is set. Cleared by writing in the SPITX register or if
finished transmission disabling the SPI.
0 SPITX data register empty status bit. Set by writing to
SPITX to send data. This bit is set during transmission of
data. Cleared when SPITX is empty.
Table 121. SPIRX Register
Name Address Default Value Access
SPIRX 0xFFFF0A04 0x00 R
SPIRX is an 8-bit, read-only receive register.
Table 122. SPITX Register
Name Address Default Value Access
SPITX 0xFFFF0A08 0x00 W
SPITX is an 8-bit, write-only transmit register.
Table 123. SPIDIV Register
Name Address Default Value Access
SPIDIV 0xFFFF0A0C 0x1B R/W
SPIDIV is an 8-bit, serial clock divider register.
Table 124. SPICON Register
Name Address Default Value Access
SPICON 0xFFFF0A10 0x0000 R/W
SPICON is a 16-bit control register.
Table 125. SPICON MMR Bit Descriptions
Bit Description Function
15:13 Reserved N/A
12 Continuous transfer enable
Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is
available in the TX register.
CS
is asserted and remains asserted for the duration of each 8-bit serial transfer
until TX is empty. Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit
serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period.
11 Loop back enable Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode.
10 Slave MISO output enable
Set this bit to disable the output driver on the MISO pin. The MISO pin becomes open drain when this bit is
set. Clear this bit for MISO to operate as normal.
9 Clip select output enable
Set by user in master mode to disable the chip select output. cleared by user to enable the chip select
output.
P1.7 should be configured as
CS
before SPICON is configured as a master when the chip select output
enabled is also selected.
8 SPIRX overflow overwrite enable
Set by user, the valid data in the RX register is overwritten by the new serial byte received. Cleared by user,
the new serial byte received is discarded.
7 SPITX underflow mode Set by user to transmit 0. Cleared by user to transmit the previous data.
6 Transfer and interrupt mode
Set by user to initiate transfer with a write to the SPITX register. Interrupt occurs only when TX is empty.
Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt occurs only when RX is full.
5 LSB first transfer enable bit Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first.
4 Reserved
3 Serial clock polarity mode bit Set by user, the serial clock idles high. Cleared by user, the serial clock idles low.
2 Serial clock phase mode bit
Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the serial
clock pulses at the end of each serial bit transfer.
1 Master mode enable bit Set by user to enable master mode. Cleared by user to enable slave mode.
0 SPI enable bit Set by user to enable the SPI. Cleared by user to disable the SPI.