Datasheet
ADT75 Data Sheet
Rev. B | Page 6 of 24
TIMING SPECIFICATIONS AND DIAGRAM
Measure the SDA and SCL timing with the input filters turned on to meet the fast mode I
2
C specification. Switching off the input filters
improves the transfer rate but has a negative effect on the EMC behavior of the part.
T
A
= T
MIN
to T
MAX
, V
DD
= 2.7 V to 5.5 V, unless otherwise noted.
Table 3.
Parameter
1
Min Typ Max Unit Test Conditions/Comments
Serial Clock Period, t
1
2.5 µs Fast mode I
2
C. See Figure 2
Data In Setup Time to SCL High, t
2
50 ns See Figure 2
Data Out Stable After SCL Low, t
3
0 0.9
2
ns Fast mode I
2
C. See Figure 2
Data Out Stable After SCL Low, t
3
0 3.45
2
µs Standard mode I
2
C. See Figure 2
SDA Low Setup Time to SCL Low (Start Condition), t
4
50 ns See Figure 2
SDA High Hold Time After SCL High (Stop Condition), t
5
50 ns See Figure 2
SDA and SCL Rise Time, t
6
300 ns Fast mode I
2
C. See Figure 2
SDA and SCL Rise Time, t
6
1000 ns Standard mode I
2
C. See Figure 2
SDA and SCL Fall Time, t
7
300 ns See Figure 2
Capacitive Load for each Bus Line, C
B
400
pF
1
Guaranteed by design and characterization; not production tested.
2
This time has to be met only if the master does not stretch the low period of the SCL signal.
SCL
t
4
t
2
t
1
t
3
t
5
t
7
SDA
DATA IN
SDA
DATA OUT
t
6
05326-002
Figure 2. SMBus/I
2
C Timing Diagram